Owner's manual

5-10
Ultra-High-Speed Flash
Microcontroller User’s Guide
Page Mode 1 External Timing—Pages 1:0 = 10b (Four Cycles) (continued)
Figure 5-11 shows execution of the INC direct instruction (2 byte, two or three cycles) for the cases where an extra memory cycle is
not (INC DPL) and is (INC DPS) required.
Figure 5-12 illustrates execution of the ACALL instruction whose destination address is on a different 256-byte page. Therefore, the
second execution cycle of the ACALL instruction is a page-miss memory cycle that requires an ALE signal toggle to be used in order
to latch a new address MSB.
HIT
SYSCLK
ALE
PSEN
PORT 2
PORT 0
ACALL
71
MISS HITHIT
LSB ADDRESS MSB ADDRESS LSB ADDRESS LSB ADDRESS
LSB ADDRESS
33
Figure 5-12. Four-Cycle Page Mode: ACALL – (Page Miss)
SYSCLK
ALE
PSEN
PORT 2
PORT 0
MSB ADDRESS
INC DPL INC DPS
05
8205 86 E0 E0
LSB ADDRESSLSB ADDRESSLSB ADDRESS
HIT HIT HIT
STALL
HIT
Figure 5-11. Four-Cycle Page Mode 1: INC Direct (Two Cycles) – INC Direct (Three Cycles)
Maxim Integrated