Owner's manual

Ultra-High-Speed Flash
Microcontroller User’s Guide
P1.7–0
Bits 7–0
INT5
Bit 7
INT4
Bit 6
INT3
Bit 5
INT2
Bit 4
TXD1
Bit 3
RXD1
Bit 2
T2EX
Bit 1
T2
Bit 0
General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all
the pins have an alternative function listed below. Each of the functions is controlled by several
other SFRs. The associated Port 1 latch bit must contain a logic 1 before the pin can be used in its
alternate function capacity.
External Interrupt 5. A falling edge on this pin causes an external interrupt 5 if enabled.
External Interrupt 4. A rising edge on this pin causes an external interrupt 4 if enabled.
External Interrupt 3. A falling edge on this pin causes an external interrupt 3 if enabled.
External Interrupt 2. A rising edge on this pin causes an exter
nal interrupt 2 if enabled.
Serial Port 1 Transmit. This pin transmits the serial port 1 data in serial port modes 1, 2, 3 and
emits the synchr
onizing clock in serial port mode 0.
Serial Port 1 Receive. This pin receives the serial port 1 data in serial port modes 1, 2, 3 and is a
bidirectional data transfer pin in serial port mode 0.
Timer 2 Capture/Reload T
rigger. A 1-to-0 transition on this pin causes the value in the T2 regis-
ters to be transferred into the captur
e registers if enabled by EXEN2 (T2CON.3). When in auto-
reload mode, a 1-to-0 transition on this pin reloads the Timer 2 registers with the value in RCAP2L
and RCAP2H if enabled by EXEN2 (T2CON.3).
Timer 2 External Input. A 1-to-0 transition on this pin causes T
imer 2 increment or decrement bit
depending on the timer configuration.
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset,* = See description.
External Interrupt Flag (EXIF)
76543210
SFR 91h IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGS
RW-0 RW-0 RW-0 RW-0 R-* R-* RW-* RT-0
IE5
Bit 7
IE4
Bit 6
IE3
Bit 5
IE2
Bit 4
External Interrupt 5 Flag. This bit is set when a falling edge is detected on INT5. This bit must be
cleared manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 4 Flag. This bit is set when a rising edge is detected on INT4. This bit must be
cleared manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 3 Flag. This bit is set when a falling edge is detected on INT3. This bit must be
clear
ed manually by software. Setting this bit in software causes an interrupt if enabled.
External Interrupt 2 Flag. This bit is set when a rising edge is detected on INT2. This bit must be
cleared manually by software. Setting this bit in software causes an interrupt if enabled.
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Port 1 (P1)
76543210
SFR 90h
P1.7
INT5
P1.6
INT4
P1.5
INT3
P1.4
INT2
P1.3
TXD1
P1.2
RXD1
P1.1
T2EX
P1.0
T2
RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1
Maxim Integrated
4-20