Owner's manual

4-17
GATE
Bit 7
C/T
Bit 6
M1, M0
Bits 5, 4
Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment.
0 = Timer 1 clocks when TR1 = 1, regardless of the state of INT.
1 = Timer 1 clocks only when TR1 = 1 and INT1 = 1.
Timer 1 Counter/Timer Select.
0 = Timer 1 is incremented by internal clocks.
1 = Timer 1 is incremented by pulses on T1 when TR1 (TCON.6) is 1.
Timer 1 Mode Select. These bits select the operating mode of Timer 1.
GATE
Bit 3
C/T
Bit 2
M1, M0
Bits 1, 0
Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment.
0 = Timer 0 clocks when TR0 = 1, regardless of the state of INT0.
1 = Timer 0 clocks only when TR0 = 1 and INT0 = 1.
Timer 0 Counter/Timer Select.
0 = Timer incremented by internal clocks.
1 = Timer 1 is incremented by pulses on T0 when TR0 (TCON.4) is 1.
Timer 0 Mode Select. These bits select the operating mode of Timer 0. When Timer 0 is in mode
3, TL0 is star
ted/stopped by TR0 and TH0 is started/stopped by TR1. Run control from Timer 1 is
then provided by the Timer 1 mode selection.
Table 4-6. Timer 0 Mode Selection
M1
M0
MODE
0 0 Mode 0: 8 bits with 5-bit prescale
0 1 Mode 1: 16 bits
1 0 Mode 2: 8 bits with autoreload
1 1 Mode 3: Timer 0 is two 8-bit counters
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Timer 0 LSB (TL0)
7 6 5 4 3 2 1 0
SFR 8Ah TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
TL0.7–0
Bits 7–0
Timer 0 LSB. This register contains the least significant byte of Timer 0.
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Timer Mode Control (TMOD)
7 6 5 4 3 2 1 0
SFR 89h GATE C/T M1 M0 GATE C/T M1 M0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Table 4-5. Timer 1 Mode Selection
M1
M0
MODE
0
0 Mode 0: 8 bits with 5-bit prescale
0 1 Mode 1: 16 bits
1
0 Mode 2: 8 bits with autoreload
1
1 Mode 3: Timer 1 is halted, but holds its count
Ultra-High-Speed Flash
Microcontroller User’s Guide
Maxim Integrated