Owner manual

Secure Microcontroller User’s Guide
3 of 187
9.11 RANDOM NUMBER GENERATOR .................................................................................................. 81
9.12 S
ECURITY SUMMARY BY PART .................................................................................................... 81
9.13 A
PPLICATION: ADVANCED SECURITY TECHNIQUES ...................................................................... 82
10. RESET CONDITIONS ....................................................................................................... 85
10.1 R
ESET SOURCES ....................................................................................................................... 85
10.1.1 Power-On Reset ................................................................................................................................... 87
10.1.2 No-V
LI
Power-On Reset ....................................................................................................................... 88
10.1.3 External Reset ...................................................................................................................................... 88
10.1.4 Watchdog Timer Reset ........................................................................................................................ 88
10.2 M
EMORY MAP ............................................................................................................................ 89
10.3 I
NTERRUPTS .............................................................................................................................. 90
10.4 T
IMERS ...................................................................................................................................... 90
10.5 T
RANSIENT VOLTAGE PROTECTION ............................................................................................. 91
11. INTERRUPTS ................................................................................................................... 92
11.1 I
NTERRUPT SOURCES ................................................................................................................ 92
11.2 E
XTERNAL INTERRUPTS .............................................................................................................. 93
11.3 T
IMER INTERRUPTS .................................................................................................................... 93
11.4 S
ERIAL PORT INTERRUPTS ......................................................................................................... 93
11.5 P
OWER-FAIL WARNING INTERRUPT ............................................................................................ 94
11.6 S
IMULATED INTERRUPTS ............................................................................................................ 94
11.7 I
NTERRUPT PRIORITIES .............................................................................................................. 96
11.8 I
NTERRUPT ACKNOWLEDGE ........................................................................................................ 97
12. PARALLEL I/O ................................................................................................................. 99
12.1 O
UTPUT FUNCTIONS ................................................................................................................ 102
12.2 I
NPUT FUNCTION ...................................................................................................................... 103
12.3 R
EAD-MODIFY-WRITE INSTRUCTIONS ....................................................................................... 104
12.4 R
EPROGRAMMABLE PERIPHERAL CONTROLLER (RPC) ............................................................. 104
12.5 RPC
INTERRUPTS .................................................................................................................... 106
12.6 RPC
PROTOCOL ...................................................................................................................... 107
12.7 DMA
OPERATION ..................................................................................................................... 107
13. PROGRAMMABLE TIMERS .......................................................................................... 109
13.1 F
UNCTIONAL DESCRIPTION ....................................................................................................... 109
13.2 M
ODE 0 ................................................................................................................................... 111
13.3 M
ODE 1 ................................................................................................................................... 111
13.4 M
ODE 2 ................................................................................................................................... 112
13.5 M
ODE 3 ................................................................................................................................... 114
14. SERIAL I/O ..................................................................................................................... 115
14.1 F
UNCTION DESCRIPTION .......................................................................................................... 115
14.2 B
AUD RATE GENERATION ......................................................................................................... 118
14.3 S
YNCHRONOUS OPERATION (MODE 0) ...................................................................................... 119
14.4 A
SYNCHRONOUS OPERATION ................................................................................................... 120
15. CPU TIMING ................................................................................................................... 130
15.1 O
SCILLATOR ............................................................................................................................ 130
15.2 I
NSTRUCTION TIMING ............................................................................................................... 131
15.3 E
XPANDED PROGRAM MEMORY TIMING .................................................................................... 132
15.4 E
XPANDED DATA MEMORY TIMING ........................................................................................... 135
16. PROGRAM LOADING .................................................................................................... 137
16.1 I
NVOKING THE BOOTSTRAP LOADER ......................................................................................... 137
16.2 I
NVOKING THE BOOTSTRAP LOADER ON DS5000 SERIES DEVICES ............................................ 138
16.3 I
NVOKING THE BOOTSTRAP LOADER ON DS5001/DS5002 SERIES DEVICES .............................. 138
16.4 E
XITING THE LOADER ............................................................................................................... 139
16.5 S
ERIAL PROGRAM LOAD MODE ................................................................................................. 141