Owner manual

Secure Microcontroller User’s Guide
2 of 187
TABLE OF CONTENTS
1. INTRODUCTION ................................................................................................................. 7
1.1 I
MPORTANT NOTICE REGARDING DISCONTINUED DS2251T/DS2252T .............................................. 7
1.2 S
OFTWARE SECURITY ..................................................................................................................... 7
1.3 P
RODUCT DESCRIPTION .................................................................................................................. 9
1.4 I
NTRODUCTION TO THE DS5250 HIGH-SPEED SECURE MICROCONTROLLER ................................... 10
2. SELECTOR GUIDE .......................................................................................................... 12
3. SECURE MICROCONTROLLER ARCHITECTURE ........................................................ 13
3.1 B
US ORGANIZATION ...................................................................................................................... 13
3.2 CPU
REGISTERS ........................................................................................................................... 13
4. PROGRAMMER’S GUIDE ................................................................................................ 18
4.1 S
ECURE MICROCONTROLLER MEMORY ORGANIZATION .................................................................. 18
4.1.1 Internal Registers ................................................................................................................................. 19
4.1.2 Program and Data Memory .................................................................................................................. 20
4.2 DS5000
SERIES MEMORY ORGANIZATION ..................................................................................... 21
4.3 DS5000
MEMORY MAP CONTROL .................................................................................................. 23
4.4 DS5001/DS5002
MEMORY ORGANIZATION ................................................................................... 24
4.5 DS5001/DS5002
MEMORY-MAPPED PERIPHERALS ....................................................................... 27
4.6 DS5001/DS5002
MEMORY MAP CONTROL .................................................................................... 28
4.7 L
OADING AND RELOADING PROGRAM MEMORY .............................................................................. 28
4.8 S
PECIAL FUNCTION REGISTERS ..................................................................................................... 33
4.9 I
NSTRUCTION SET ......................................................................................................................... 48
4.10 A
DDRESSING MODES ................................................................................................................. 48
4.11 P
ROGRAM STATUS FLAGS .......................................................................................................... 50
5. MEMORY INTERCONNECT ............................................................................................ 51
6. LITHIUM/BATTERY BACKUP ......................................................................................... 58
6.1 D
ATA RETENTION .......................................................................................................................... 58
7. POWER MANAGEMENT ................................................................................................. 62
7.1 I
DLE MODE .................................................................................................................................... 62
7.2 S
TOP MODE .................................................................................................................................. 64
7.3 V
OLTAGE MONITORING CIRCUITRY ................................................................................................ 64
7.4 P
OWER-FAIL INTERRUPT ............................................................................................................... 64
7.5 T
OTAL POWER FAILURE ................................................................................................................. 65
7.6 P
ARTIAL POWER FAILURES ............................................................................................................ 66
8. SOFTWARE CONTROL ................................................................................................... 68
8.1 T
IMED ACCESS .............................................................................................................................. 68
8.2 W
ATCHDOG TIMER ........................................................................................................................ 70
8.3 CRC
MEMORY VERIFICATION ........................................................................................................ 71
8.3.1 Automatic CRC on Power-Up Feature ................................................................................................. 71
9. FIRMWARE SECURITY ................................................................................................... 74
9.1 S
ECURITY LOCK ............................................................................................................................ 74
9.2 RAM
MEMORY .............................................................................................................................. 75
9.3 E
NCRYPTED MEMORY ................................................................................................................... 76
9.4 E
NCRYPTION ALGORITHM .............................................................................................................. 78
9.5 E
NCRYPTION KEY .......................................................................................................................... 78
9.6 E
NCRYPTION KEY SELECTION AND LOADING .................................................................................. 78
9.7 D
UMMY BUS ACCESS .................................................................................................................... 79
9.8 O
N-CHIP VECTOR RAM ................................................................................................................. 79
9.9 S
ELF-DESTRUCT INPUT ................................................................................................................. 80
9.10 M
ICROPROBE/DIE TOP COATING ................................................................................................ 81