Datasheet

MAX9880A Evaluation Kit
Evaluates: MAX9880A
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Status Register
The Status group box provides labels that report the
state of the Status register bits (CLD, SLD, ULK, JDET)
and the SHDN bit (see Table 7). The other status regis-
ters (Jack Status, AUX) are reported on their individual
windows. Jack Status can be monitored by selecting
the JACKSNS block, and the AUX registers are report-
ed on the Auxiliary Configuration window, which is
accessed by selecting the AUX[15:0] block. See the
Jack Detection and ADC Input Register sections.
Interrupt Enables
Hardware interrupts are enabled/disabled by setting/
clearing the interrupt item listed under the Options |
Interrupt Enables menu item. In order for a status reg-
ister flag to be reported on the device’s open-drain IRQ
pin, the corresponding interrupt enable bit must be set.
Otherwise, the flag is only reported as a software inter-
rupt in the Status group box.
Digital Audio Interface and Clock Registers
The system and digital audio clock registers and digital
audio interface registers are all accessed by selecting
the Digital Interface 1 or Digital Interface 2 blocks
on the Digital Audio tab. The DAI1 clock control and
configuration registers are controlled through the digital
audio interface 1 windows and the DAI2 clock control
and configuration registers are controlled through the
digital audio interface 2 windows. Each of the digital
audio interfaces has two windows, basic and advanced.
The System Clock register (0x05) is accessed from both
digital audio interface windows.
The first time selecting a Digital Interface block, on the
Digital Audio tab, opens the digital audio interface’s
basic window. The interface’s advanced window is ini-
tially accessed by pressing the Advanced Mode button
on the digital audio interface basic windows. Similarly,
the basic window can be accessed by pressing the
Basic Mode button on the advanced window. Any sub-
sequent clicking of the Digital Interface blocks opens
either the basic or advanced interface window, which-
ever window was active last.
See the Digital Audio Interface 1 - Basic and Digital
Audio Interface 1 - Advanced sections and refer to the
Clock Control and Digital Audio Interface sections of the
MAX9880A IC data sheet for a complete understanding
on how to use and configure the digital audio interfaces.
Figure 7a. USB Stereo Audio DAC (Enable Window)
Figure 7b. USB Stereo Audio DAC (Disable Window)
Table 7. Status Bits
Table 8. DAI_ Basic Window Controls
LABEL BIT (REGISTER)
Full Scale CLD (0x00)
Volume Slew Complete SLD (0x00)
PLL Unlock ULK (0x00)
Jack Detect JDET (0x00)
SHDN (shutdown)
SHDN (0x27)
CONTROL DESCRIPTION
MCLK Frequency edit box Derives the PSCLK setting from the MCLK frequency.
Master/Slave drop-down list Sets the master mode bit (MAS_).
Audio Selection drop-down list
Configures the connection between S1/S2 pins and DAI1/DAI2 signal paths (SEL_,
SDOEN_, SDIEN_ bits).
LRCLK Frequency drop-down list Configures clock control when the interface is set for normal or PLL mode.
Configuration drop-down list Configures the delay mode, TDM mode, and TDM slot.
Configure button Configures the U1 device and closes the window.
Advanced Mode button Opens the digital audio interface’s advanced window.
Cancel button Closes the window without configuring the U1 device.