Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
58 ______________________________________________________________________________________
CS
SCLK
DIN
DOUT
HIGH-Z
R/W ADDR9 ADDR0 UNUSED4 UNUSED0
D7 D0
1 DATA BYTE
Figure 12. Reading 1 Byte of Data from the MAX9880A
SCLK
DIN
DOUT
HIGH-Z
R/W ADDR9 ADDR0 UNUSED4 UNUSED0
D7 D0
1 DATA BYTE
1 DATA BYTE
CS
D7 D0
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 13. Reading n Bytes of Data from the MAX9880A
SMBus is a trademark of Intel Corp.
do not change until the transfer is complete. The DOUT
output is high impedance when writing the register
address bits. If the correct register address is decod-
ed, DOUT is driven low at the first rising clock edge
after the first unused bit.
Figure 12 illustrates the proper frame format for reading
1 byte of data from the MAX9880A.
When reading data from the MAX9880A, the address
pointer autoincrements by one register address if CS is
held low after reading the first 8 data bits. For each
subsequent eight clock cycles, a byte of data is read.
This autoincrement feature allows a master to read
sequential registers within one continuous SPI register
address range from 0x200 to 0x227. The register
address does not autoincrement if a read is initiated at
a register address lower than 0x200. If the register
address increments beyond 0x227, the DOUT output is
high impedance. Figure 13 illustrates the proper format
for reading multiple bytes of data.
I
2
C Serial Interface
The MAX9880A features an I
2
C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX9880A and
the master at clock rates up to 400kHz. Figure 14
shows the 2-wire interface timing diagram. The master
generates SCL and initiates data transfer on the bus.
The master device writes data to the MAX9880A by
transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or repeated
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the MAX9880A is 8 bits long and is
followed by an acknowledge clock pulse. A master
reading data from the MAX9880A transmits the proper
slave address followed by a series of nine SCL pulses.
The MAX9880A transmits data on SDA in sync with the
master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read