Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
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CS
SCLK
DIN
DOUT
t
CSS
t
CH
t
DH
t
DS
t
DO
t
DZ
t
DEN
t
CL
t
CSH
t
CP
t
CSW
Figure 10. SPI Interface Timing Diagram
CS
SCLK
DIN
DOUT
HIGH-Z
R/W ADDR9 ADDR0 UNUSED4 UNUSED0 D7 D0
1 DATA BYTE
Figure 11. Writing 1 Byte of Data to the MAX9880A
Serial Peripheral Interface (SPI)
Chip Select (CS)
The MAX9880A SPI interface is active only when CS is
low. When CS is high, the MAX9880A configures the
DOUT output for high impedance and resets the inter-
nal SPI logic. If CS goes high in the middle of an SPI
transfer, all the data is discarded. When CS is low,
unless the register address is correctly decoded by the
MAX9880A, the DOUT output is high impedance.
Serial Clock (SCLK)
The SPI master provides the SCLK signal to clock the
SPI interface. SCLK has an upper frequency limit of
25MHz. The MAX9880A samples the DIN input data on
the falling edge of SCLK and changes the output data
on the rising edge of SCLK. The MAX9880A ignores
SCLK transitions when CS is high.
Serial-Data In (DIN) and Serial-Data Out (DOUT)
The SPI frame is organized into 24 bits. The first 16 bits
consist of the R/W enable bit, followed by the 10 regis-
ter address bits and 5 unused bits. The next 8 bits are
data bits, sent most significant bit first.
For an SPI write transfer, write a 1 to the R/W bit, fol-
lowed by the 10 register address bits, 5 unused bits,
then the 8 data bits.
Figure 11 illustrates the proper frame format for writing
one byte of data to the MAX9880A. Additional 24-bit
frames can be sent while CS remains low. The DOUT
output is high impedance during a write operation.
For an SPI read transfer, write a zero to the R/W bit, fol-
lowed by the 10 register address bits and 5 unused
bits. Any data sent after the register address bits are
ignored. The internal contents of the register being read