Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
56 ______________________________________________________________________________________
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Enable LNLEN LNREN LOLEN LOREN DALEN DAREN ADLEN ADREN 0x26
System Shutdown SHDN 0 0 0 XTEN XTOSC 0 0 0x27
BITS FUNCTION
LNLEN
Left-Line Input Enable. Enables the left-line input preamp and automatically enables the left and right
headphone amplifiers. If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and
right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
LNREN
Right-Line Input Enable. Enables the right-line input preamp and automatically enables the right headphone
amplifiers.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
LOLEN Left-Line Output Enable. Enables the left-line output.
LOREN Right-Line Output Enable. Enables the right-line output.
DALEN
Left DAC Enable. Enables the left DAC and automatically enables the left and right headphone amplifiers. If
DAREN = 0, the left DAC signal is also routed to the right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
DAREN Right DAC Enable. Enables the right DAC. Right DAC operation requires DALEN = 1.
ADLEN Left ADC Enable.
ADREN
Right ADC Enable. Enabling the right ADC must be done in the same I
2
C write operation that enables the left
ADC. The right ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must
be toggled to disable the right ADC in this case. Right ADC operation requires ADLEN = 1.
SHDN Shutdown. Places the device in low power shutdown mode.
XTEN
Crystal Clock Enable
1 = Output of crystal oscillator and buffer routed to the clock prescaler. MCLK input disabled.
0 = MCLK input routed to the clock prescaler. Crystal oscillator and buffer disabled.
XTOSC
Crystal Clock Source
1 = Disables the internal crystal oscillator. Provide an external clock on X1.
0 = Enables the internal crystal oscillator. Attach a crystal between X1 and X2. XTOSC is ignored if XTEN = 0.
Table 25. Power Management Register
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Revision ID REV 0x14
Revision ID REV 0xFF
Table 26. Revision Code Register
Grayed boxes = Not used.
Note: Register addresses listed are for I
2
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Note: Register addresses listed are for I
2
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.