Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
50 ______________________________________________________________________________________
Digital Microphone Input
The MAX9880A can accept audio from up to two digi-
tal microphones. When using digital microphones, the
left analog microphone input is retasked as a digital
microphone input. The right analog microphone input is
still available to allow a combination of analog and digi-
tal microphones to be used. Figure 7 shows the digital
microphone interface timing diagram.
DIGMICCLK
DIGMICDATA
t
SU, MIC
t
HD, MIC
t
SU, MIC
t
HD, MIC
LEFT RIGHT LEFT RIGHT
1/f
MICCLK
Figure 7. Digital Microphone Timing Diagram
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Microphone MICCLK DIGMICL DIGMICR 0 0 0 MBIAS 0x23
BITS FUNCTION
MICCLK
Digital Microphone Clock
00 = PCLK/8
01 = PCLK/6
10 = 64f
S
(high jitter clock)
11 = Reserved
Digital Left/Right Microphone Enable
DIGMICL DIGMICR LEFT ADC INPUT RIGHT ADC INPUT
0 0 ADC input mixer ADC input mixer
0 1
Line input (left analog
microphone unavailable)
Right digital microphone
1 0 Left digital microphone ADC input mixer
1 1 Left digital microphone Right digital microphone
DIGMICL/
DIGMICR
Note: The left analog microphone input is never available when DIGMICL or DIGMICR = 1.
MBIAS
Microphone Bias Output Voltage
Set MBIAS = 0 for nominal output of 1.52V (V
MICVDD
= 1.8V)
Set MBIAS = 1 for nominal output of 2.2V (V
MICVDD
= 3V)
Table 19. Digital Microphone Input Register
Grayed boxes = Not used.
Note: Register addresses listed are for I
2
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.