Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
46 ______________________________________________________________________________________
Microphone Inputs
Two differential microphone inputs and a low noise 1.5V
microphone bias for powering the microphones are
provided by the MAX9880A. In typical applications, the
left microphone records a voice signal and the right
microphone records a background noise signal. In
applications that require only one microphone, use the
left microphone input and disable the right ADC. The
microphone signals are amplified by two stages of gain
and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable gain amplifier (PGA)
adjustable from 0dB to 20dB in 1dB steps. Zero-cross-
ing detection is included on the PGA to minimize zipper
noise while making gain changes. See Figure 6 for a
detailed diagram of the microphone input structure.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
Left Microphone Gain 0 PALEN PGAML 0x20
Right Microphone Gain 0 PAREN PGAMR 0x21
BITS FUNCTION
PALEN/
PAREN
Left/Right Microphone Preamplifier Gain. Enables the microphone circuitry and sets the preamplifier gain.
00 = Disabled
01 = 0dB
10 = +20dB
11 = +30dB
Table 16. Microphone Input Registers
MICLN
MICLP
MICBIAS
PGA
PGA
-
PREAMP
MICRN
ADC
L
ADC
R
MICRP
1.5V
0/20/30dB
0dB TO +20dB
0dB TO +20dB
V
REG
V
REG
0/20/30dB
PREAMP
MAX9880A
Figure 6. Microphone Input Block Diagram
Grayed boxes = Not used.
Note: Register addresses listed are for I
2
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.