Datasheet

MAX9880A

Low-Power, High-Performance

Dual I

S Stereo Audio Codec

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ADDRESS

(SEE NOTE)

Configuration SPDMCLK SPDML SPDMR 0 0 0 0 0x12

Input MIXSPDML MIXSPDMR 0x13

BITS FUNCTION

SPDMCLK

SPDM Clock Rate (SPDMCLK)

00 = SPDMCLK is set to PCLK/8.

01 = SPDMCLK is set to PCLK6.

10 = SPDMCLK is set to PCLK/4.

11 = Reserved

SPDML/SPDMR

0 = Disables SPDM data.

1 = Enables SPDM data.

SPDM Input Mixers. Selects and mixes the audio source(s) for the SPDM output according to following

information.

MIXSPDML/MIXSPDMR SOURCE

1xxx DAI1 left-channel data

x1xx DAI1 right-channel data

xx1x DAI2 left-channel data

MIXSPDML/

MIXSPDMR

xxx1 DAI2 right-channel data

Table 11. SPDM Output Registers

Grayed boxes = Not used.

Note: Register addresses listed are for I

C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not

accessible through SPI.

The MAX9880A supports stereo PDM outputs. The PDM

signals consist of PDM data outputs (SPDMDATA) and a

clock output (SPDMCLK). The mixer at the input to the

PDM modulators allows a mix/mux of the audio digital data

stream from the digital audio ports SDINS1 and SDINS2.

Figure 5 shows the SPDM interface timing diagram.

SPDMCLK

SPDMDATA LEFT CH RIGHT CH LEFT CH RIGHT CH

DLY, DSD

Figure 5. SPDM Timing Diagram