Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
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BITS FUNCTION
BCLK Select. Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL =
010, unless sharing the bus with multiple devices.
BSEL DESCRIPTION
000 Off (BCLK output held low)
001 64x LRCLK (192x internal clock divided by 3)
010 48x LRCLK (192x internal clock divided by 4)
011 128x LRCLK (Note: Not a valid BSEL2 choice when DHF = 1.)
100 PCLK/2
101 PCLK/4
110 PCLK/8
BSEL1/2
111 PCLK/16
TDM Slot Select. Selects the time slot to use for left/right data according to the following information when
operating in time-division multiplex mode.
SLOT DESCRIPTION
00 Time slot 1
01 Time slot 2
10 Time slot 3
SLOTL1/2
SLOTR1/2
11 Time slot 4
Slot Data Delay (SLOTDLY1/SLOTDLY2)
In TDM Mode: Configures the data delay for each slot in TDM mode of operation according to the following
information.
In Non-TDM Mode (TDM = 0): SLOTDLY[1:0] does not have any effect.
SLOTDLY1/2[3:0] DESCRIPTION
0xxx Data for slot 4 begins immediately.
1xxx Data for slot 4 delayed 1 BCLK cycle.
x0xx Data for slot 3 begins immediately.
x1xx Data for slot 3 delayed 1 BCLK cycle.
xx0x Data for slot 2 begins immediately.
xx1x Data for slot 2 delayed 1 BCLK cycle.
xxx0 Data for slot 1 begins immediately.
SLOTDLY1/2
xxx1 Data for slot 1 delayed 1 BCLK cycle (not valid when FSW = 1).
DHF
DAC High Sample Rate Mode (DHF) (Valid only for DAI2 audio path)
1 = LRCLK is greater than 50kHz. 4x FIR interpolation filter used.
0 = LRCLK is less than 50kHz. 8x FIR interpolation filter used.
Table 7. Digital Audio Interface Registers (continued)