Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
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REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
(SEE NOTE)
DAI1 CONFIGURATION
Interface Mode A MAS1 WCI1 BCI1 DLY1 HIZOFF1 TDM1 FSW1 0 0x08
Interface Mode B DL1 SEL1 SDOEN1 SDIEN1 DMONO1 BSEL1 0x09
Time-Division Multiplex SLOTL1 SLOTR1 SLOTDLY1[3:0] 0x0A
DAI2 CONFIGURATION
Interface Mode A MAS2 WCI2 BCI2 DLY2 HIZOFF2 TDM2 FSW2 WS2 0x0D
Interface Mode B DL2 SEL2 SDOEN2 SDIEN2 DHF BSEL2 0x0E
Time-Division Multiplex SLOTL2 SLOTR2 SLOTDLY2[3:0] 0x0F
BITS FUNCTION
MAS1/2
Master Mode
0 = The MAX9880A operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9880A operates in master mode with LRCLK and BCLK configured as outputs.
WCI1/2
LRCLK Invert (TDM1/2 = 0)
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
BCI1/2
BCLK Invert
In master and slave modes:
0 = SDIN is latched into the part on the rising edge of BCLK. SDOUT transitions immediately after the rising edge
of BCLK.
1 = SDIN is latched into the part on the falling edge of BCLK. SDOUT transitions immediately after the falling
edge of BCLK.
In master mode:
0 = LRCLK changes state immediately after the rising edge of BCLK.
1 = LRCLK changes state immediately after the falling edge of BCLK.
DLY1/2
Delay Mode. DLY1/2 have two different functions in TDM and non-TDM mode.
In Non-TDM Mode (TDM1/TDM2 = 0): The functionality is as follows:
1 = The most significant bit of an audio word is latched at the second BCLK edge after the LRCLK transition.
0 = The most significant bit of an audio word is latched at the first BCLK edge after the LRCLK transition.
In TDM Mode (TDM1/TDM2 = 1): The functionality is as follows:
1 = The HOLD time on the SDOUT output is increased to be greater than 150ns.
0 = The HOLD time on the SDOUT output is the default (greater than 20ns but less than 150ns).
HIZOFF1/2
SDOUT High-Impedance Mode
0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9880A,
allowing SDOUT to be shared by other devices.
1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9880A.
Note: High-impedance mode is intended for use when TDM = 1.
Table 7. Digital Audio Interface Registers
Grayed boxes = Not used.
Note: Register addresses listed are for I
2
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.