Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
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BITS FUNCTION
PSCLK
MCLK Prescaler. Divides MCLK down to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz. PCLK = MCLK.
10 = Select if MCLK is between 20MHz and 40MHz. PCLK = MCLK/2.
11 = Select if MCLK is greater than 40MHz. PCLK = MCLK/4.
Exact Integer Modes. Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or
16kHz sample rates.
FREQ1[3:0] PCLK (MHz) LRCLK (kHz) PCLK/LRCLK
0x00
Normal or PLL mode
0x1–0x7 Reserved Reserved Reserved
0x8
0x9
12
12
8
16
1500
750
0xA
0xB
13
13
8
16
1625
812.5
0xC
0xD
16
16
8
16
2000
1000
0xE
0xF
19.2
19.2
8
16
2400
1200
FREQ1
Modes 0x8 to 0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK
ratio cannot be guaranteed, use PLL mode instead.
PLL1/PLL2
PLL Mode Enable
0 = (Valid for slave and master mode) The frequency of LRCLK is set by the NI divider bits. In master mode,
the MAX9880A generates LRCLK using the specified divide ratio. In slave mode, the MAX9880A expects
an LRCLK as specified by the divide ratio.
1 = (Valid for slave mode only) A digital PLL locks on to any externally supplied LRCLK signal.
RLK1/RLK2
Rapid Lock Mode. To enable rapid lock mode set NI_ to the nearest desired ratio and set RLK_ = 1 before
enabling the interface.
NI1/NI2
Normal Mode LRCLK Divider. When PLL = 0, the frequency of LRCLK is determined by NI. See Table 6 for
common NI values.
For LRCLK = 8kHz to 48kHz operation (DHF = 0 for DAI2):
NI = (65,536 x 96 x f
LRCLK
)/f
PCLK
f
LRCLK
= LRCLK frequency
f
PCLK
= Prescaled internal MCLK frequency (PCLK)
For LRCLK > 50kHz operation (DHF = 1 for DAI2):
NI = (65,536 x 48 x f
LRCLK
)/f
PCLK
f
LRCLK
= LRCLK frequency
f
PCLK
= Prescaled internal MCLK frequency (PCLK)
Table 5. System and Audio Clock Registers (continued)