Datasheet

MAX9880A
Low-Power, High-Performance
Dual I
2
S Stereo Audio Codec
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Pin Description (continued)
PIN
TQFN-EP WLP
NAME FUNCTION
23 E8 LINL Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor.
24 F8 LINR Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor.
25 F7 LOUTR Right-Line Output
26 E7 LOUTL Left-Line Output
27 E6, F6 PGND Headphone Power Ground
29 E5 ROUTP
Positive Right-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
30 F5 ROUTN
Negative Right-Channel Headphone Output. Unused in capacitorless and
single-ended mode.
31 F4 LOUTN
Negative Left-Channel Headphone Output. Common headphone return in
capacitorless mode. Unused in single-ended mode.
32 E4 LOUTP
Positive Left-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
34 E3, F3 PVDD Headphone Power Supply. Bypass to PGND with a 1µF capacitor.
36 F2 DVDDS1
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1µF
capacitor.
37 F1 SDOUTS1 S1 Digital Audio Serial-Data ADC Output
38 D3 SDINS1 S1 Digital Audio Serial-Data DAC Input
39 E1 LRCLKS1
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample
rate clock and determines whether the audio data on SDINS1 is routed to the left
or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
40 E2 BCLKS1
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the
MAX9880A is in slave mode and an output when in master mode.
41 D1 MCLK Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
42 D2 SDOUTS2 S2 Digital Audio Serial-Data ADC Output
43 C1 SDINS2 S2 Digital Audio Serial-Data DAC Input
44 C2 LRCLKS2
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample
rate clock and determines whether the audio data on SDINS2 is routed to the left
or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
45 C3 BCLKS2
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the
MAX9880A is in slave mode and an output when in master mode.
46 B1 DVDD
Digital Power Supply. Supply for the digital core and I
2
C/SPI interface. Bypass to
DGND with a 1.0µF capacitor.
47 A1 DGND Digital Ground
— — EP Exposed Pad. Connect the exposed thermal pad to AGND.