Datasheet
MAX9867
Ultra-Low Power Stereo Audio Codec
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Power Management
The MAX9867 includes complete power management
control to minimize power usage. The DAC and both
ADC can be independently enabled so that only the
required circuitry is active. Toggle the SHDN bit when-
ever a configuration change is made. Table 17 is the
power-management register.
Table 17. Power-Management Register
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
System Shutdown SHDN LNLEN LNREN 0 DALEN DAREN ADLEN ADREN 0x17
BITS FUNCTION
SHDN
Shutdown
Places the device in low-power shutdown mode.
LNLEN
Left-Line Input Enable
Enables the left-line input preamp and automatically enables the left and right headphone amplifiers.
If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and right headphone
amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
LNREN
Right-Line Input Enable
Enables the right-line input preamp and automatically enables the right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
DALEN
Left DAC Enable
E nab l es the l eft D AC and autom ati cal l y enab l es the l eft and r i g ht head p hone am p l i fi er s. If D ARE N = 0, the
l eft D AC si g nal i s al so r outed to the r i g ht head p hone am p l i fi er .
Note: Control of the right headphone amplifier can be overridden by HPMODE.
DAREN
Right DAC Enable
Enabling the right DAC must be done in the same I
2
C write operation that enables the left DAC. Right
DAC operation requires DALEN = 1.
ADLEN Left ADC Enable
ADREN
Right ADC Enable
Enabling the right ADC must be done in the same I
2
C write operation that enables the left ADC. The right
ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must be toggled
to disable the right ADC in this case. Right ADC operation requires ADLEN = 1.
Revision Code
The MAX9867 includes a revision code to allow easy
identification of the device revision. The revision code is
0x42. See Table 18 for the revision code register.
Table 18. Revision Code Register
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
Revision REV 0xFF