Datasheet

MAX9867
I
2
C Registers
The MAX9867 audio codec is completely controlled
through software using an I
2
C interface. The power-on
default setting is complete shutdown, requiring that the
internal registers be programmed to activate the device.
See Table 1 for the device’s complete register map.
I
2
C Slave Address
The MAX9867 responds to the slave address 0x30 for
all write commands and 0x31 for all read operations.
Ultra-Low Power Stereo Audio Codec
22 ______________________________________________________________________________________
REGISTER B7 B6 B5 B4 B3 B2 B1 B0
REGISTER
ADDRESS
POWER-
ON RESET
STATE
STATUS
Status (Read Only) CLD SLD ULK 0 0 0 JDET 0 0x00 —
Jack Sense (Read Only) LSNS JKSNS JKMIC 0 0 0 0 0 0x01 —
AUX High (Read Only) AUX[15:8] 0x02 —
AUX Low (Read Only) AUX[7:0] 0x03 —
Interrupt Enable ICLD ISLD IULK 0 0 SDODLY IJDET 0 0x04 0x00
CLOCK CONTROL
System Clock 0 0 PSCLK FREQ 0x05 0x00
Stereo Audio Clock
Control High
PLL NI[14:8] 0x06 0x00
Stereo Audio Clock
Control Low
NI[7:1]
RLK/
NI[0]
0x07 0x00
DIGITAL AUDIO INTERFACE
Interface Mode MAS WCI BCI DLY HIZOFF TDM 0 0 0x08 0x00
Interface Mode 0 0 0 LVOLFIX DMONO BSEL 0x09 0x00
DIGITAL FILTERING
Codec Filters MODE AVFLT 0 DVFLT 0x0A 0x00
LEVEL CONTROL
Sidetone DSTS 0 DVST 0x0B 0x00
DAC Level 0 DACM DACG DACA 0x0C 0x00
ADC Level AVL AVR 0x0D 0x00
Left-Line Input Level 0 LILM 0 0 LIGL 0x0E 0x00
Right-Line Input Level 0 LIRM 0 0 LIGR 0x0F 0x00
Left Volume Control 0 VOLLM VOLL 0x10 0x00
Right Volume Control 0 VOLRM VOLR 0x11 0x00
Left Microphone Gain 0 PALEN PGAML 0x12 0x00
Right Microphone Gain 0 PAREN PGAMR 0x13 0x00
CONFIGURATION
ADC Input MXINL MXINR AUXCAP AUXGAIN AUXCAL AUXEN 0x14 0x00
Microphone MICCLK DIGMICL DIGMICR 0 0 0 0 0x15 0x00
Mode DSLEW VSEN ZDEN 0 JDETEN HPMODE 0x16 0x00
POWER MANAGEMENT
System Shutdown SHDN LNLEN LNREN 0 DALEN DAREN ADLEN ADREN 0x17 0x00
Revision REV 0xFF 0x42
Table 1. I
2
C Register Map