Datasheet

The DAC begins its soft-start routine after being enabled
and after receiving 32 LRCLK cycles. All internal filters
are initialized and the DAC gain gradually ramps to
maximum. The MAX9850’s headphone output level is
determined by the headphone amplifier volume setting.
Mute the audio outputs before powering down the
MAX9850 by setting MUTE to 1 (register 0x2, bit B7).
Ramping the volume to its maximum attenuation is an
alternative to muting the output. VMN in the status A reg-
ister (register 0x0, bit B3) notifies the µC when the out-
puts are at maximum attenuation. Disable the
headphone and line outputs once the audio is fully atten-
uated. Headphone and line outputs can be disabled
within 50µs without any audible clicks or pops, once the
audio is fully attenuated. Place the MAX9850 in shut-
down after the outputs are disabled.
Stereo Speakerphone
The MAX9850 can be combined with a stereo speaker
amplifier to create a complete speakerphone playback
solution. The MAX9701, or another Maxim stereo
speaker amplifier, can be used to drive the speakers
while the MAX9850’s integrated DirectDrive headphone
amplifier drives the headphones (see Figure 12).
Configure GPIO to output high when a headphone is not
connected and low when the headphone is connected.
Connect GPIO to the SHDN control of the MAX9701.
Configure the interrupt enable register to set ALERT (reg-
ister 0x0, bit B7) when HPS changes state. The µC polls
the status A register and waits for ALERT to set when
HPS changes state. The µC changes the state of GPIO
when ALERT is set, either turning off the speaker amp
because a headphone is connected or enabling the
speaker amp when the headphone is disconnected.
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
______________________________________________________________________________________ 33
μ
C
MAX9850
MAX9701*
1.8V TO 3.6V
3.3V TO 5.5V
0.47
μ
F
AGNDDGNDPGND
PGNDSHDN
PV
SS
SV
SS
OUTR+
OUTR-
INL+
INL-
OUTL+
OUTL-
INR+
INR-
HPL
HPS
HPR
AV
DD
V
DD
PV
DD
DV
DD
DV
DD
DIGITAL
AUDIO
SOURCE
SDIN
MCLK
C1N
C1P
REF
SDA
10k
Ω
SCL
BCLK
LRCLK
*FUTURE PRODUCT—CONTACT FACTORY FOR AVAILABILITY.
1
μ
F
1
μ
F
1
μ
F
0.47
μ
F
0.47
μ
F
0.47
μ
F
0.47
μ
F
2.2
μ
F
1
μ
F
GPIO
OUTR
OUTL
Figure 12. Stereo Speakerphone