Datasheet

requires only two small ceramic capacitors (0.47µF and
2.2µF), conserving board space, reducing cost,
improving the frequency response, and THD of the
headphone amplifier. In addition to the cost and size
disadvantages, the DC-blocking capacitors required by
conventional headphone amplifiers limit low-frequency
response and decrease PSRR performance. Some
dielectrics can significantly distort the audio signal.
Volume Control
Program VOL(5:0) in the volume register (register 0x2,
bits B5–B0) to set the volume attenuation of the head-
phone amplifiers. Program VOL(5:0) to 0x00 for full vol-
ume. Minimum volume occurs at VOL(5:0) greater than
or equal to 0x28. VMN in the status A register (register
0x0, bit B3) sets to 1 when the MAX9850 output is pro-
grammed to and reaches volume step 0x3F. Figure 1
shows the attenuation profile for each VOL(5:0) value.
Volume Slew, Zero-Crossing Detect, and Mute
Set SLEW = 1 in the volume register (register 0x2, bit
B6) to enable the volume slew circuit. When SLEW = 1
headphone amplifier volume changes will slew
between programmed levels smoothly. Set the volume
slew rate with SR(1:0) in the charge-pump register
(register 0x7, bits B7 and B6). Table 1 lists the volume
slew-rate settings for each value of SR(1:0).
Set ZDEN = 1 in the general-purpose register (register
0x3, bit B0) to force volume changes and headphone
amplifier muting to occur when the audio signal is at its
zero crossing. For optimal performance, set SR(1:0) to
01. This zero-crossing detection reduces audible
clicks/pops caused when transitioning or slewing
between volume levels.
Set MUTE = 1 in the volume register (register 0x2, bit
B7) to mute the headphone amplifiers. The mute func-
tion is independent of the volume control. The pro-
grammed volume settings are not reset when mute is
enabled. With the zero-crossing detection and volume
slew enabled, the Mute command mutes the output
after the first zero crossing or after a 200ms timeout
(SR = 01).
Mono Mode
Set MONO = 1 in the general-purpose register (register
0x3, bit B2) to enable mono mode. In mono mode, HPR
is disabled, the left and right audio channels are
summed and output on HPL. The 6dB attenuation
ensures that the summed signal amplitude does not
overdrive headphone amplifiers. SMONO in the status B
register (register 0x1, bit B4) sets to 1 when the
MAX9850 is in mono mode.
Configuring the Headphone and Line Outputs
Set HPEN and LNOEN in the enable register (register
0x5, bits B3 and B2) equal to 1 to enable the head-
phone outputs (HPR and HPL). Set HPEN or LNOEN =
0 to disable the headphone outputs.
The headphone amplifier inputs are driven from the out-
puts of the line amplifier. Disabling the line out by setting
LNOEN = 0 in the enable register (register 0x5, bit B2),
deprives the headphone amplifiers of an input signal and
disables the headphone outputs (HPR and HPL).
The internal charge pump must be enabled to operate
the headphone and line outputs. Enable the charge
pump by programming CPEN(1:0) = 11 in the enable
register (register 0x5, bits B5 and B4). See the Charge
Pump section for more details.
Headphone Sense Input (HPS)
The headphone sense input (HPS) monitors the head-
phone jack, and automatically disables the headphone
amplifiers based upon the voltage applied at HPS. For
automatic headphone detection, connect HPS to the
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
______________________________________________________________________________________ 15
VOL(5:0) CODE
HEADPHONE ATTENUATION (dB)
564832 4016 248
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
-120
064
Figure 1. Headphone Amplifier Attenuation Profile
Table 1. Slew-Rate Settings
TYPICAL VOLUME SLEW RATE
SR1
SR0
FROM FULL
VOLUME TO MUTE
FROM FULL
VOLUME TO
VMN = 1 (ms)
0 0 63µs 0.1
0 1 125ms 200
1 0 63ms 100
1 1 42ms 67