Datasheet

A master reading data from the MAX9850 transmits the
proper slave address followed by a series of nine SCL
pulses. The MAX9850 transmits data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or REPEATED START condition, a
not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically greater than 500Ω, is
required on the SDA bus. SCL operates as an input only.
A pullup resistor, typically greater than 500Ω, is required
on SCL if there are multiple masters on the bus, or if the
master in a single-master system has an open-drain SCL
output. Series resistors in line with SDA and SCL are
optional. Series resistors protect the digital inputs of the
MAX9850 from high-voltage spikes on the bus lines, and
minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I
2
C bus is not busy.
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
______________________________________________________________________________________ 29
1514131211109876543210 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RIGHTLEFT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1514131211109876543210
RIGHTLEFT
LRCLK
SDIN
BCLK
LRCLK
SDIN
BCLK
LEFT-JUSTIFIED
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00000000
15X 1413121110 9 8 7 6 5 4 3 2 1 0
RIGHTLEFT
LRCLK
SDIN
BCLK
I
2
S
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00001000
RIGHT-JUSTIFIED
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00000100
15X 14131211109876543210
Figure 4. Right-Justified, and Left-Justified Audio Data Formats (Slave Mode, 16-Bit Data)
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
t
HD, STA
t
HD, STA
t
HD, STA
t
SP
t
BUF
t
SU, STO
t
LOW
t
SU, DAT
t
HD, DAT
t
HIGH
t
R
t
F
Figure 5. 2-Wire Interface Timing Diagram