Datasheet

The interrupt enable register programs the MAX9850 to
set ALERT = 1 when an event occurs. GPIO pulses
when ALERT sets if GM(1:0) is programmed with 10 or
11. Table 4 contains a list of events that can set ALERT
and their corresponding bit positions in the interrupt
enable register. Enable the interrupt for each event by
setting its bit to 1.
GPIO as an Input
The state of the GPIO input is read through SGPIO in
the status A register (register 0x0, bit B6). Set ISGPIO =
1 to allow ALERT to set when SGPIO changes state.
Internal Timing
The internal clock (ICLK) and sample rate clock
(LRCLK in master mode) are derived from MCLK. The
MAX9850’s flexible operating modes allow any desired
LRCLK sample rate to operate over a wide range of
MCLK input frequencies.
Figure 3 shows a flowchart detailing how the internal
clocks are derived from MCLK. The MAX9850 generates
ICLK by dividing the MCLK frequency. Higher ICLK fre-
quencies allow for greater DAC oversampling and SNR
performance. Dynamic range of 90dB (typ) is possible
when f
ICLK
is greater than or equal to 12MHz. Lower ICLK
frequencies may require slightly less supply current but
sacrifice dynamic range. See the SNR vs. MCLK
Frequency graph in the Typical Operating Characteristics.
ICLK is a frequency-scaled version of MCLK that is
used by the MAX9850 to clock the internal DAC circuit-
ry and generate LRCLK and BCLK when in master
mode. The charge-pump clock is derived from ICLK
when the internal charge-pump oscillator is not used.
Connect an available system clock to MCLK, see the
DAC Operating Modes section. MCLK can be supplied
from any synchronous or available asynchronous system
clock whose frequency falls within the 8.448MHz to
13MHz, or 16.896MHz to 40MHz range. Any MCLK within
these ranges allow the MAX9850 to operate at any sam-
ple rate between 8kHz to 48kHz in either a master or
slave mode of operation. Other MCLK frequencies can
still be used, but will limit the sample rate ranges that the
MAX9850 operates with as illustrated in Table 5.
Higher ICLK frequencies provide higher SNR. Always
use the highest acceptable ICLK. Sample rates other
than those listed in Table 5 can be used. The MAX9850
defaults to IC(1:0) = 0x0 at power-up.
DAC Operating Modes
Four DAC operating modes: master integer, slave integer,
master noninteger, and slave noninteger allow flexibility
for operating with various applications and virtually any
available MCLK frequency within the system. The operat-
ing modes are set with MAS in the digital audio register
(register 0xA, bit B7) and INT in the LRCLK MSB register
(register 0x8, bit B7). Table 6 shows the four modes of
operation and the equations needed to program the
MAX9850 to use the DAC modes.
The master and slave integer modes are the modes in
which DACs commonly operate. In these modes, LRCLK
is ICLK divided by an integer value. A typical application
would set MCLK equal to 256 x LRCLK. The MAX9850
requires that ICLK be an integer multiple of 16 x LRCLK
where the integer multiple is at least 10 when in master
or slave integer modes. Integer mode always provides
the maximum full-scale signal level performance com-
pared to other modes of operation. Choose integer mode
over any other mode of operation when possible.
The master noninteger mode allows for a condition
where LRCLK and ICLK may not be related by an inte-
ger value. In these modes, the MAX9850 can operate
from any available MCLK in the system.
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
______________________________________________________________________________________ 17
Table 4. Interrupt Enable Register (0x4) Events
EVENT BIT NUMBER IN REGISTER 0x4
LCK (register 0x0, bit B5) sets when the internal PLL acquires or loses frequency lock B5
SHPS (register 0x0, bit B4) sets after the headphone is inserted and the debounce time has
elapsed when the headphone amplifier is powered up and ready
B4
VMN (register 0x0, bit B3) sets when the headphone amplifier minimum volume is reached B3
IOHL or IOHR (register 0x0, bits B1 or B0) sets after an overcurrent at either HPL or HPR B0
IC(1:0)
0x0 = 1/1
0x1 = 1/2
0x2 = 1/3
0x3 = 1/4
CP(4:0)
LRCLK DIVIDER
INTERNAL CLOCK
(ICLK)
MASTER CLOCK
(MCLK)
CHARGE-PUMP
CLOCK
LRCLK*
*LRCLK IS GENERATED WHEN IN MASTER
MODE ONLY. THE DIVIDER IS SET WITH THE
LRCLK MSB AND LRCLK LSB REGISTERS.
Figure 3. Internally Generated Clock Signals Derived from MCLK