Datasheet

MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
12 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 LRCLK
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock and determines
whether the audio data on SDIN is routed to the left or right channel. LRCLK is an input when the
MAX9850 is in slave mode and an output when in master mode.
2 BCLK
Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9850 is in slave mode and an
output when in master mode.
3 SDIN Digital Audio Serial Data Input
4DV
DD
Digital Power-Supply Input. Bypass to DGND with a 1µF ceramic capacitor.
5 MCLK Master Clock Input. All internal digital clocks are derived from MCLK.
6 DGND Digital Ground
7 ADD
I
2
C Address-Select Input. Connect to AGND, AV
DD
, or SDA to select one of the three possible I
2
C
addresses.
8 GPIO
General-Purpose Input/Output. Configure GPIO as an input or an output through the GPIO register.
GPIO can perform the function of an interrupt when configured as an output. See the GPIO section.
9 INR Right-Channel Line Input. INR is mixed with the right DAC output.
10 INL Left-Channel Line Input. INL is mixed with the left DAC output.
11 OUTR Line Level Right-Channel Output. OUTR is biased at AGND.
12 OUTL Line Level Left-Channel Output. OUTL is biased at AGND.
13 REF Reference Output. Bypass to AGND with a 1µF ceramic capacitor.
14 AGND Analog Ground
15 NREG Line Output Negative Regulator Output. Bypass to AGND with a 1µF capacitor.
16 PREG Line Output Positive Regulator Output. Bypass to AGND with a 1µF capacitor.
17 AV
DD
Analog Power Supply. Bypass to AGND with a 1µF ceramic capacitor.
18 HPR Right-Channel Headphone Output. HPR is a DirectDrive output biased at AGND.
19 HPL Left-Channel Headphone Output. HPL is a DirectDrive output biased at AGND.
20 SV
SS
Headphone Amplifier Negative Power-Supply Input. Connect to PV
SS
.
21 HPS
Headphone Sense Input. Connect to the control pin of a headphone jack for automatic headphone
sensing. Float HPS if unused. See the Headphone Sense Input (HPS) section.
22 PV
SS
Inverting Charge-Pump Output. Bypass to PGND with a 2.2µF ceramic capacitor and connect to SV
SS
to provide the headphone amplifiers with a negative supply.
23 C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47µF ceramic capacitor between
C1N and C1P.
24 PGND Charge-Pump Ground
25 C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47µF ceramic capacitor between C1P
and C1N.
26 PV
DD
Charge-Pump and Headphone Amplifier Positive Power-Supply Input. Bypass to PGND with a 1µF
ceramic capacitor. Connect to AV
DD
for normal operation.
27 SCL I
2
C-Compatible Serial Clock Input
28 SDA I
2
C-Compatible Serial Data Input/Output
— EP Exposed Thermal Pad. Connect EP to AGND.