Datasheet

MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
31Maxim Integrated
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filter adds cost, size, and decreases efficiency
and THD+N performance. The ICs’ filterless modulation
scheme does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear to
recover the audio component of the square-wave output.
Because the switching frequency of the ICs is well
beyond the bandwidth of most speakers, voice coil
movement due to the switching frequency is very small.
Use a speaker with a series inductance > 10FH. Typical
8I speakers exhibit series inductances in the 20FH to
100FH range.
Power-Supply Input
V
DD
, which ranges from 2.5V to 5.5V, powers the IC,
including the speaker amplifier. Bypass V
DD
with a 0.1FF
and 10FF capacitor to GND. Some applications might
require only the 10FF bypass capacitor, making it pos-
sible to operate with a single external component. Apply
additional bulk capacitance at the ICs if long input traces
between V
DD
and the power source are used.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Good grounding improves audio perfor-
mance and prevents switching noise from coupling into
the audio signal.
Use wide, low-resistance output traces. As load imped-
ance decreases, the current drawn from the device
outputs increases. At higher current, the resistance of
the output traces decreases the power delivered to the
load. For example, if 2W is delivered from the speaker
output to a 4I load through 100mI of total speaker
trace, 1.904W is being delivered to the speaker. If power
is delivered through 10mI of total speaker trace, 1.951W
is being delivered to the speaker. Wide output, supply,
and ground traces also improve the power dissipation of
the ICs.
The ICs are inherently designed for excellent RF immu-
nity. For best performance, add ground fills around all
signal traces on top or bottom PCB planes.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability testing
results, refer to the Application Note 1891: Wafer-Level
Packaging (WLP) and Its Applications. Figure 20 shows
the dimensions of the WLP balls used on the ICs.
Figure 19. Left/2 + Right/2 PCM Operation with 6dB Gain Figure 20. MAX98355A/MAX98355B WLP Ball Dimensions
OUTP
OUTN
GAIN
V
DD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
BCLK
LRCLK
R
LARGE
(300kI)**
DIN
GND
*LEFT AND RIGHT CHANNELS SUMMED WHEN GPIO IS HIGH.
**300kI ASSUMES V
GPIO
= 1.8V.
THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW.
MAX98355A
MAX98355B
GPIO*
CODEC
BIT CLOCK
FRAME CLOCK
DATA OUT
B2 A2
A1
C1
C3
B1
C2
B3
A3
0.21mm
0.24mm