Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsLinear IC - Audio amplifier 1-channel (mono) Class D WLP 9

MAX98355A/MAX98355B

PCM Input Class D Audio Power Amplifiers

19-6278; Rev 1; 8/13

General Description

The MAX98355A/MAX98355B are digital pulse-code

modulation (PCM) input Class D power amplifiers that

provide Class AB audio performance with Class D effi-

ciency. These ICs offer five selectable gain settings

(3dB, 6dB, 9dB, 12dB, and 15dB) set by a single gain-

select input (GAIN).

The digital audio interface is highly flexible with the

MAX98355A supporting I

S data and the MAX98355B

supporting left-justified data. Both ICs support time divi-

sion multiplexed (TDM) data. The digital audio interface

accepts sample rates ranging from 8kHz to 96kHz for all

supported data formats. The ICs can be configured to

produce a left channel, right channel, or left/2 + right/2

output from the stereo input data. The ICs operate using

16/24/32-bit data for I

S and left justified modes as well

as 16-bit data with up to four slots when using TDM

mode. The ICs eliminate the need for the external MCLK

signal that is typically used for PCM communication. This

reduces EMI and possible board coupling issues in addi-

tion to reducing the size and pin count of the ICs.

The ICs also feature a very high wideband jitter tolerance

(12ns typ) on BCLK and LRCLK to provide robust operation.

Active emissions-limiting, edge-rate limiting, and over-

shoot control circuitry greatly reduce EMI. A filterless

spread-spectrum modulation scheme eliminates the

need for output filtering found in traditional Class D

devices and reduces the component count of the solution.

The ICs are available in a 9-pin WLP package (1.345mm

x 1.435mm x 0.64mm) and are specified over the -40NC

to +85NC temperature range.

Applications

Cellular Phones

Tablets

Portable Media Players

Notebook Computers

Features

S Single-Supply Operation (2.5V to 5.5V)

S 3.2W Output Power into 4I at 5V

S 2.4mA Quiescent Current

S 92% Efficiency (R

= 8I, P

OUT

= 900mW,

= 3.7V)

S 25µV

RMS

Output Noise (A

= 15dB)

S Low 0.013% THD+N at 1kHz

S No MCLK Required

S Sample Rates of 8kHz to 96kHz

S Supports Left, Right, or Left/2 + Right/2 Outputs

S Sophisticated Edge Rate Control Enables

Filterless Class D Outputs

S 77dB PSRR at 217Hz

S Low RF Susceptibility Rejects TDMA

Noise from GSM Radios

S Extensive Click-and-Pop Reduction Circuitry

S Robust Short-Circuit and Thermal Protection

S Available in Space-Saving Package:

1.345mm x 1.435mm WLP (0.4mm Pitch)

Ordering Information appears at end of data sheet.

Functional Diagram appears at end of data sheet.

For related parts and recommended products to use with this part,

refer to www.maximintegrated.com/MAX98355A.related.

Simplified Block Diagram

EVALUATION KIT AVAILABLE

DAC

CLASS D

OUTPUT

STAGE

DIGITAL

AUDIO

INTERFACE

PCM

INPUT

GAIN

CONTROL

SHUTDOWN

AND

CHANNEL

SELECT

MAX98355A

MAX98355B

For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Summary of content (34 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers General Description The MAX98355A/MAX98355B are digital pulse-code modulation (PCM) input Class D power amplifiers that provide Class AB audio performance with Class D efficiency. These ICs offer five selectable gain settings (3dB, 6dB, 9dB, 12dB, and 15dB) set by a single gainselect input (GAIN).
PAGE 2
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers LIST OF FIGURES Figure 1. I2S Audio Interface Timing Diagram (MAX98355A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Left-Justified Audio Interface Timing Diagram (MAX98355B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. TDM Audio Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers ABSOLUTE MAXIMUM RATINGS VDD, LRCLK, BCLK, and DIN to GND.....................-0.3V to +6V All Other Pins to GND............................... -0.3V to (VDD + 0.3V) Continuous Current In/Out of VDD/GND/OUT_.................. Q1.6A Continuous Input Current (all other pins)......................... Q20mA Duration of OUT_ Short Circuit to GND or VDD…......Continuous Duration of OUTP Short to OUTN..............................
PAGE 5
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS THD+N = 10%, gain = 12dB Output Power (Note 3) POUT THD+N = 1%, gain = 12dB Total Harmonic Distortion + Noise THD+N MIN TYP ZSPK = 4I + 33FH 3.
PAGE 6
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AUDIO MODE FIR LOWPASS FILTER (30kHz < LRCLK < 50kHz) Passband Cutoff Stopband Cutoff fPLP Ripple limit cutoff 0.
PAGE 7
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.
PAGE 8
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers tBCLK tBCLKH tBCLKL BCLK (INPUT) tSYNCSET tSYNCHOLD LRCLK (INPUT) tSETUP tHOLD DIN (INPUT) LSB MSB LSB MSB Figure 1. I2S Audio Interface Timing Diagram (MAX98355A) tBCLK tBCLKH tBCLKL BCLK (INPUT) tSYNCSET tSYNCHOLD LRCLK (INPUT) tSETUP tHOLD DIN (INPUT) LSB MSB LSB MSB Figure 2.
PAGE 9
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) General SHUTDOWN CURRENT vs. SUPPLY VOLTAGE QUIESCENT CURRENT vs. SUPPLY VOLTAGE MAX98355A/B toc02 3.0 0.6 SHUTDOWN CURRENT (µA) 3.5 QUIESCENT CURRENT (mA) 0.7 MAX98355A/B toc01 4.0 2.5 2.0 1.5 1.0 0.
PAGE 10
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) f = 6kHz -60 f = 1kHz -70 -80 f = 100Hz 0.01 0.1 1 -50 f = 6kHz -60 -70 f = 1kHz 1 -100 10 100 0.001 0.01 0.
PAGE 11
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY -50 -60 POUT = 150mW -80 -40 -50 -60 -70 POUT = 250mW POUT = 600mW 1k 10k -100 100k 10 1.5 THD+N = 10% 1.0 0.
PAGE 12
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) OUTPUT POWER vs. SUPPLY VOLTAGE THD+N = 10% 1.0 THD+N = 1% 0.5 0 THD+N = 10% 2.5 2.0 1.5 THD+N = 1% 1.0 3.0 3.5 4.0 4.5 5.0 3.0 4.0 4.5 5.0 50 40 30 10 0 0 0.1 0.2 0.3 0.4 0.5 0.
PAGE 13
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) EFFICIENCY vs. OUTPUT POWER 50 40 30 80 60 50 40 30 20 0 0 0 2.0 MAX98355A-B toc27 100 PSRR (dB) 60 40 20 20 f = 1kHz ZSPK = 8I + 68µH 3.0 3.5 4.0 4.
PAGE 14
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.
PAGE 15
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Typical Operating Characteristics (continued) (VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) INBAND OUTPUT SPECTRUM -20 AMPLITUDE (dBV) -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 -140 -140 2 4 6 8 10 12 14 16 18 20 0 2 4 6 FREQUENCY (kHz) INBAND OUTPUT SPECTRUM BCLK = 1.
PAGE 16
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Pin Configuration TOP VIEW BUMP SIDE DOWN + MAX98355A MAX98355B SD_MODE VDD OUTP A1 A2 A3 DIN GAIN OUTN B1 B2 B3 BCLK GND LRCLK C1 C2 C3 WLP Pin Description PIN NAME A1 SD_MODE A2 VDD A3 OUTP B1 DIN FUNCTION Shutdown and Channel Select. Determines left, right, or left/2 + right/2 mix and also used for shutdown. See Table 5.
PAGE 17
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Detailed Description The MAX98355A/MAX98355B are digital PCM input Class D power amplifiers. The MAX98355A accepts standard I2S data through DIN, BCLK, and LRCLK while the MAX98355B accepts left justified data through the same inputs. Both versions can accept 16-bit TDM data with up to four slots. These devices eliminate the need for an external MCLK signal that is typically required for PCM data transmission.
PAGE 18
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers PCM Timing Characteristics The MAX98355A follows standard I2S timing by setting a delay of one BCLK cycle after the LRCLK transition before the beginning of a new data word (Figure 4 and Figure 5). The MAX98355B follows the left justified timing specification by aligning the LRCLK transitions with the beginning of a new data word (Figure 6 and Figure 7). Figure 8 and Figure 9 show TDM operation, in which a frame-sync pulse is used for LRCLK.
PAGE 19
Maxim Integrated DIN BCLK LRLCK LEFT D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT IGNORED D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I2S: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RLARGE DIN BCLK LRLCK LEFT D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I2S: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RSMALL DIN BCLK LRLCK I2S: 24-BIT DATA
PAGE 20
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers LEFT JUSTIFIED: 16-BIT DATA, SD_MODE = LOGIC-HIGH LRCLK RIGHT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D6 D5 D4 D3 D2 D1 D0 D15 D14 IGNORED LEFT JUSTIFIED: 16-BIT DATA, SD_MODE = PULLUP THROUGH RSMALL LRCLK RIGHT LEFT BCLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7
PAGE 21
Maxim Integrated D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT IGNORED D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT DIN BCLK LRCLK D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT LEFT JUSTIFIED: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RLARGE DIN BCLK LRCLK LEFT JUSTIFIED: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RSMALL DIN BCLK L
PAGE 22
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = LOGIC-HIGH R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 IGNORED R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 IGNORED TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 IGNORED IGNORED TDM:
PAGE 23
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = LOGIC-HIGH R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 IGNORED R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 IGNORED TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 IGNORED IGNORED TDM:
PAGE 24
Maxim Integrated Y0 L15 L14 L13 L12 L11 L10 L9 IGNORED Y1 L8 L7 L6 L5 L4 L3 L2 Y1 L8 IGNORED Y0 L15 L14 L13 L12 L11 L10 L9 L7 L6 L5 L4 L3 L2 DIN BCLK LRCLK Y0 L15 L14 L13 L12 L11 L10 L9 IGNORED Y1 L8 L7 L6 L5 L3 L2 L1 L1 L1 L0 R15 R14 R13 R12 R11 R10 R9 L0 R15 R14 R13 R12 R11 R10 R9 L0 R15 R14 R13 R12 R11 R10 R9 LEFT AND RIGHT AVERAGED L4 TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE DIN BCLK LRCLK TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLU
PAGE 25
Maxim Integrated Y1 Y0 L15 L14 L13 L12 L11 L10 L9 IGNORED L8 L7 L6 L5 L4 L3 L2 L1 Y1 L8 IGNORED Y0 L15 L14 L13 L12 L11 L10 L9 L7 L6 L5 L4 L3 L2 L1 DIN BCLK LRCLK Y0 L15 L14 L13 L12 L11 L10 L9 IGNORED Y1 L8 L7 L6 L5 L4 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 L0 R15 R14 R13 R12 R11 R10 R9 L0 R15 R14 R13 R12 R11 R10 R9 LEFT AND RIGHT AVERAGED L3 TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE DIN BCLK LRCLK TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLU
PAGE 26
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers SD_MODE and Shutdown Operation Standby Mode If BCLK stops toggling, the ICs automatically enter standby mode. In standby mode, the Class D speaker is turned off and the outputs go into a high-impedance state, ensuring that unwanted current is not transferred to the load during this condition.
PAGE 27
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers When the devices are configured in left-channel mode (SD_MODE is directly driven to logic-high by the control interface), take care to avoid violating the Absolute Maximum Ratings limits for SD_MODE. Ensuring that VDD is always greater than VDDIO is one way to prevent SD_MODE from violating the Absolute Maximum Ratings limits. If this is not possible in the application (e.g., if VDD < 3.0V and VDDIO = 3.
PAGE 28
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Maxim’s spread-spectrum modulation mode flattens wideband spectral components while proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency. The ICs’ spread-spectrum modulator randomly varies the switching frequency by Q10kHz around the center frequency (300kHz). Above 10MHz, the wideband spectrum looks like noise for EMI purposes (Figure 14).
PAGE 29
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Applications Information 2.5V TO 5.5V 2.5V TO 5.5V 10µF 0.1µF SD_MODE GAIN B2 CODEC GPIO* BCLK BIT CLOCK FRAME CLOCK LRCLK DIN DATA OUT A1 C3 B1 0.1µF SD_MODE GAIN B2 CODEC VDD A2 A3 C1 10µF MAX98355A MAX98355B GPIO* OUTP BCLK BIT CLOCK B3 OUTN FRAME CLOCK LRCLK DIN DATA OUT C2 GND A1 VDD A2 A3 C1 C3 B1 MAX98355A MAX98355B B3 OUTP OUTN C2 GND *RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
PAGE 30
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers 2.5V TO 5.5V 10µF 0.1µF VDD GAIN SD_MODE BCLK LRCLK DIN A1 B2 A2 A3 C1 OUTP MAX98355A MAX98355B C3 B3 B1 OUTN C2 GND CODEC *RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH. THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW. GPIO* BIT CLOCK 2.5V TO 5.5V FRAME CLOCK 10µF DATA OUT RSMALL (76.8kI)** 0.
PAGE 31
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The filter adds cost, size, and decreases efficiency and THD+N performance. The ICs’ filterless modulation scheme does not require an output filter.
PAGE 32
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Functional Diagram 2.5V TO 5.5V 10µF 0.1µF VDD GAIN A2 MAX98355A MAX98355B LRCLK C3 BCLK C1 DIN B1 SD_MODE A1 DIGITAL AUDIO INTERFACE B2 INTERPOLATOR DAC CLASS D OUTPUT STAGE A3 OUTP B3 OUTN C2 GND Ordering Information PART MAX98355AEWL+ MAX98355BEWL+ TEMP RANGE PIN-PACKAGE -40NC to +85NC -40NC to +85NC 9 WLP 9 WLP +Denotes a lead(Pb)-free/RoHS-compliant package.
PAGE 33
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
PAGE 34
MAX98355A/MAX98355B PCM Input Class D Audio Power Amplifiers Revision History REVISION NUMBER REVISION DATE 0 5/12 Initial release 1 8/13 Updated Electrical Characteristics table with lower tolerances; updated Typical Operating Characteristics; updated style throughout DESCRIPTION PAGES CHANGED — 1, 3–7, 9–18, 26, 31, 33 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product.