Datasheet

Maxim Integrated │ 91
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Table 15. Recommended Compensation Filter Settings for f
PCLK
= 11.2896MHz
Table 16. Recommended Compensation Filter Settings for f
PCLK
= 12MHz
Table 14. Digital Microphone Configuration
ADDRESS: 0x14
DESCRIPTION
BIT NAME TYPE POR
7
DMIC_COMP[3:0] R/W
0
Digital Microphone Compensation Filter Conguration
0000–1000: Figure 8 details the available compensation lter congurations.
1001–1111: Congures the compensation lter to a pass through response.
The compensation lter response scales with the sample rate up to the Nyquist
bandwidth limit (f
S
/2). Automatically decoded in quick conguration mode.
6 0
5 0
4 0
3 — — — —
2 — — — —
1
DMIC_FREQ[1:0]
R/W 0
Digital Microphone Frequency Range Conguration
00: f
DMC
< 3.5MHz 10: 4.5MHz ≤ f
DMC
01: 3.5MHz ≤ f
DMC
< 4.5MHz 11: Reserved
If any of the system clock quick conguration bits in register 0x04 are set, then the
frequency range conguration is automatically decoded.
0 R/W 0
f
PCLK
= f
MCLK
/PSCLK (See Table 34) RECOMMENDED DMIC_COMP SETTING BY SAMPLE RATE (kHz)
MICCLK DIVIDER f
DMC
(MHz) DMIC_FREQ 8 16 32 44.1 48
0 f
PCLK
/2 5.6448 2 7 8 3 3 3
1 f
PCLK
/3 3.7632 1 7 8 2 2 2
2 f
PCLK
/4 2.8224 0 7 8 3 3 3
3 f
PCLK
/5 2.25792 0 7 8 6 6 6
4 f
PCLK
/6 1.8816 0 7 8 3 3 3
5 f
PCLK
/8 1.4112 0 7 8 3 3 3
f
PCLK
= f
MCLK
/PSCLK (See Table 34) RECOMMENDED DMIC_COMP SETTING BY SAMPLE RATE (kHz)
MICCLK DIVIDER f
DMC
(MHz) DMIC_FREQ 8 16 32 44.1 48
0 f
PCLK
/2 6 2 7 8 3 3 3
1 f
PCLK
/3 4 1 7 8 2 2 2
2 f
PCLK
/4 3 0 7 8 3 3 3
3 f
PCLK
/5 2.4 0 7 8 5 5 6
4 f
PCLK
/6 2 0 7 8 3 3 3
5 f
PCLK
/8 1.5 0 7 8 3 3 3