Datasheet

Maxim Integrated │ 89
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Table 11. Microphone Bias Level Configuration Register
Table 12. Digital Microphone Clocks for Commonly Used Master Clocks Settings
Table 13. Digital Microphone Enable
ADDRESS: 0x12
DESCRIPTION
BIT NAME TYPE POR
7 — — — —
6 — — — —
5 — — — —
4 — — — —
3 — — — —
2 — — — —
1
MBVSEL[1:0] R/W
0
Microphone Bias Level Conguration
00: 2.2V 10: 2.55V
01: 2.4V 11: 2.8V
0 0
Master Clock Frequency (f
MCLK
) 10MHz 11.2896MHz 12MHz 12.288MHz 13/26MHz 19.2MHz
Approximate Digital
Microphone Clock
Frequency (f
DMC
)
f
PCLK
/2 5.0MHz 5.645MHz 6.0MHz 6.144MHz 6.5MHz —
f
PCLK
/3 3.333MHz 3.763MHz 4.0MHz 4.096MHz 4.333MHz 6.4MHz
f
PCLK
/4 2.5MHz 2.822MHz 3.0MHz 3.072MHz 3.25MHz 4.8MHz
f
PCLK
/5 2.0MHz 2.258MHz 2.4MHz 2.458MHz 2.6MHz 3.84MHz
f
PCLK
/6 1.667MHz 1.882MHz 2.0MHz 2.048MHz 2.167MHz 3.2MHz
f
PCLK
/8 1.25MHz 1.411MHz 1.5MHz 1.536MHz 1.625MHz 2.4MHz
ADDRESS: 0x13
DESCRIPTION
BIT NAME TYPE POR
7 — — — —
6
DMICCLK[2:0] R/W
0
Digital Microphone Clock Rate Conguration
000: f
DMC
= f
PCLK
/2 100: f
DMC
= f
PCLK
/6
001: f
DMC
= f
PCLK
/3 101: f
DMC
= f
PCLK
/8
010: f
DMC
= f
PCLK
/4 110: Reserved
011: f
DMC
= f
PCLK
/5 111: Reserved
5 0
4 0
3 — — — —
2 — — — —
1 DIGMICR R/W 0
Digital Microphone Clock and Right Channel Enable
0: Right record channel uses on-chip ADC.
1: Right record channel uses digital microphone input.
Digital microphone clock (DMC) is enabled once both data channels are enabled.
0 DIGMICL R/W 0
Digital Microphone Clock and Left Channel Enable
0: Left record channel uses on-chip ADC.
1: Left record channel uses digital microphone input.
Digital microphone clock (DMC) is enabled once both data channels are enabled.