Datasheet
Maxim Integrated
│
88
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Figure 7. Digital Microphone Input Functional Diagram
Analog Microphone Bias Voltage
The device features a regulated, low noise microphone
bias output (MICBIAS) that can be configured to power
a wide range of external microphone devices. To enable
the microphone bias output, set MBEN in the input enable
register (Table 7). When the device is powered and the
microphone bias is disabled (MBEN is low or the device
is in shutdown), MICBIAS is placed in a high-impedance
state. The microphone bias voltage can be set by the soft-
ware to any one of 4 voltages (2.2V, 2.4V, 2.55V, or 2.8V)
by programming the Microphone Bias Level Configuration
register (Table 11).
Digital Microphone Inputs
One pair of microphone inputs (IN1/IN2) can also be
configured to interface to up to two digital microphones
(Figure 7). The record path DSP is automatically switched
to accept the appropriate digital microphone data channel
when enabled (Figure 13). Both channels (left and right)
must be enabled to use the digital microphone interface.
When both channels are enabled, the digital microphone
interface provides a digital microphone clock on IN2/DMC
and accepts PDM data on IN1/DMD. A single digital micro-
phone input cannot be paired with a single analog micro-
phone input. Left channel data is accepted on falling clock
edges while the right channel data is accepted on the rising
clock edges (see Figure 4 for timing requirements).
To avoid any potential clipping and distortion, always
enable the record path DC blocking filters to remove any
built-in DC offsets when using a digital microphone input
(AHPF, Table 21). The record path biquad filter and digital
gain and level control stages can also be applied to digital
microphone input signals.
Digital Microphone Clock Conguration
The digital microphone clock frequency (f
DMC
) can be
configured to any one of 6 settings using MICCLK[2:0]
(Table 13). The digital microphone clock is derived from
a PCLK divider, with available settings ranging incremen-
tally from f
PCLK
/2 to f
PCLK
/8. This wide range of available
digital microphone clock frequencies is intended to sup-
port both current and next generation digital microphones.
Table 12 lists the resulting clock frequencies for common-
ly used master clock (and resulting PCLK) frequencies.
DIGMICR
ADC
LEFT
MIXER
ADC
LEFT
ADC
RIGHT
MIXER
ADC
RIGHT
PCLK
DMDL
ADCL
DMDR
ADCR
DIGMICL
MICCLK[2:0]
DIGITAL
MICROPHONE
CONTROL
IN2/DMC
IN1/DMD
IN3
IN4
IN5
MICBIAS
(WLP ONLY)
IN6
DIGITAL
MIC
LEFT
MUX
DIGITAL
MIC
RIGHT
MUX
LEFT
RECORD
PATH DSP
RIGHT
RECORD
PATH DSP
FLEXSOUND
TECHNOLOGY
DSP
DAI
MAX98090