Datasheet

Maxim Integrated │ 81
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Table 3. Bias Control Register
Table 4. DAC and Headphone Performance Mode Control Register
Power and Performance Management
The device includes comprehensive power management
to allow the disabling of unused blocks to minimize sup-
ply current. In addition to this, the available power modes
provide a software configurable choice between highest
performance and reduced power consumption.
Device Performance Conguration
The Bias Control register (Table 3) selects the method
used to derive the common-mode reference voltage. A
common-mode bias created by resistive division (from the
AVDD supply) facilitates lower overall power consumption
by disabling the bandgap reference circuit. However, this
type of BIAS reference has the disadvantage of scaling
with the AVDD supply voltage (and thus also has reduced
PSRR). When derived from a bandgap reference, BIAS
is constant regardless of the supply voltage, but the addi-
tional circuitry increases power consumption.
The ADC, DAC, and headphone playback all have option-
al high-performance modes (Tables 4 and 5). In each
case, these modes trade additional power consumption
for enhanced performance. The ADC also has optional
ADDRESS: 0x42
DESCRIPTION
BIT NAME TYPE POR
7 — — — —
6 — — — —
5 — — — —
4 — — — —
3 — — — —
2 — — — —
1 — — — —
0 BIAS_MODE R/W 0
Select source for BIAS.
0: BIAS derived from resistive division.
1: BIAS created by bandgap reference.
ADDRESS: 0x43
DESCRIPTION
BIT NAME TYPE POR
7 — — — —
6 — — — —
5 — — — —
4 — — — —
3 — — — —
2 — — — —
1 PERFMODE R/W 0
Performance Mode
Selects DAC to headphone playback performance mode:
1: Low power headphone playback mode.
0: High performance headphone playback mode.
0 DACHP R/W 0
DAC High-Performance Mode
0: DAC settings optimized for lowest power consumption.
1: DAC settings optimized for best performance.