Datasheet

Maxim Integrated │ 75
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION REGISTER CONTENTS
POR
STATE
ADDR NAME R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
HEADPHONE (HP) CONTROL REGISTERS
0x29 LEFT HP MIXER R/W — — MIXHPL[5:0] 0x00
0x2A RIGHT HP MIXER R/W — — MIXHPR[5:0] 0x00
0x2B HP CONTROL R/W — —
MIXHP
RSEL
MIXHP
LSEL
MIXHPRG[1:0] MIXHPLG[1:0] 0x00
0x2C LEFT HP VOLUME R/W HPLM — — HPVOLL[4:0] 0x1A
0x2D RIGHT HP VOLUME R/W HPRM — — HPVOLR[4:0] 0x1A
SPEAKER (SPK) CONFIGURATION REGISTERS
0x2E LEFT SPK MIXER R/W — — MIXSPL[5:0] 0x00
0x2F RIGHT SPK MIXER R/W —
SPK_
SLAVE
MIXSPR[5:0] 0x00
0x30 SPK CONTROL R/W — — — — MIXSPRG[1:0] MIXSPLG[1:0] 0x00
0x31 LEFT SPK VOLUME R/W SPLM — SPVOLL[5:0] 0x2C
0x32
RIGHT SPK
VOLUME
R/W SPRM — SPVOLR[5:0] 0x2C
DYNAMIC RANGE CONTROL (DRC) CONFIGURATION REGISTERS
0x33 DRC TIMING R/W DRCEN DRCRLS[2:0] — DRCATK[2:0] 0x00
0x34
DRC
COMPRESSOR
R/W DRCCMP[2:0] DRCTHC[4:0] 0x00
0x35 DRC EXPANDER R/W DRCEXP[2:0] DRCTHE[4:0] 0x00
0x36 DRC GAIN R/W — — — DRCG[4:0] 0x00
RECEIVER (RCV OR EARPIECE) AND LINE OUTPUT (LOUT) REGISTERS
0x37 RCV/LOUTL MIXER R/W — — MIXRCVL[5:0] 0x00
0x38
RCV/LOUTL
CONTROL
R/W — — — — — — MIXRCVLG[1:0] 0x00
0x39
RCV/LOUTL
VOLUME
R/W RCVLM — — RCVLVOL[4:0] 0x15
0x3A LOUTR MIXER R/W LINMOD — MIXRCVR[5:0] 0x00
0x3B LOUTR CONTROL R/W — — — — — — MIXRCVRG[1:0] 0x00
0x3C LOUTR VOLUME R/W RCVRM — — RCVRVOL[4:0] 0x15
JACK DETECT AND ENABLE REGISTERS
0x3D JACK DETECT R/W JDETEN JDWK — — — — JDEB[1:0] 0x00
0x3E INPUT ENABLE R/W — — — MBEN LINEAEN LINEBEN ADREN ADLEN 0x00
0x3F OUTPUT ENABLE R/W HPREN HPLEN SPREN SPLEN RCVLEN RCVREN DAREN DALEN 0x00
0x40 LEVEL CONTROL R/W — — — — —
ZDEN VS2EN VSEN
0x00