Datasheet

Maxim Integrated │ 74
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Table 1. MAX98090 Control Register Map (continued)
REGISTER DESCRIPTION REGISTER CONTENTS
POR
STATE
ADDR NAME R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADC PATH AND CONFIGURATION REGISTERS
0x15 LEFT ADC MIXER R/W — MIXADL[6:0] 0x00
0x16 RIGHT ADC MIXER R/W — MIXADR[6:0] 0x00
0x17
LEFT RECORD
LEVEL
R/W — AVLG[2:0] AVL[3:0] 0x03
0x18
RIGHT RECORD
LEVEL
R/W — AVRG[2:0] AVR[3:0] 0x03
0x19
RECORD BIQUAD
LEVEL
R/W — — — — AVBQ[3:0] 0x00
0x1A RECORD SIDETONE R/W DSTS[1:0] — DVST[4:0] 0x00
CLOCK CONFIGURATION REGISTERS
0x1B SYSTEM CLOCK R/W — — PSCLK[1:0] — — — — 0x00
0x1C CLOCK MODE R/W FREQ[3:0] — — — USE_MI 0x00
0x1D
CLOCK RATIO
NI MSB
R/W — NI[14:8] 0x00
0x1E
CLOCK RATIO
NI LSB
R/W NI[7:0] 0x00
0x1F
CLOCK RATIO
MI MSB
R/W MI[15:8] 0x00
0x20
CLOCK RATIO
MI LSB
R/W MI[7:0] 0x00
0x21 MASTER MODE R/W MAS — — — — BSEL[2:0] 0x00
INTERFACE CONTROL REGISTERS
0x22
INTERFACE
FORMAT
R/W — — RJ WCI BCI DLY WS[1:0] 0x00
0x23 TDM CONTROL R/W — — — — — — FSW TDM 0x00
0x24 TDM FORMAT R/W SLOTL[1:0] SLOTR[1:0] SLOTDLY[3:0] 0x00
0x25
I/O
CONFIGURATION
R/W — — LTEN LBEN DMONO HIZOFF SDOEN SDIEN 0x00
0x26
FILTER
CONFIGURATION
R/W MODE AHPF DHPF DHF — — — — 0x80
0x27
DAI PLAYBACK
LEVEL
R/W DVM — DVG[1:0] DV[3:0] 0x00
0x28
EQ PLAYBACK
LEVEL
R/W — — —
EQCLP
DVEQ[3:0] 0x00