Datasheet

Maxim Integrated │ 73
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Table 1. MAX98090 Control Register Map
Note: Register bits in bold italics are for the WLP package only.
REGISTER DESCRIPTION REGISTER CONTENTS
POR
STATE
ADDR NAME R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RESET/STATUS/INTERRUPT REGISTERS
0x00 SOFTWARE RESET W SWRESET — — — — — — — 0x00
0x01 DEVICE STATUS CoR CLD SLD ULK — — JDET DRCACT DRCCLP 0x00
0x02 JACK STATUS R — — — — — LSNS JKSNS — 0x00
0x03 INTERUPT MASKS R/W ICLD ISLD IULK — — IJDET IDRCACT IDRCCLP 0x04
QUICK SETUP REGISTERS
0x04 SYSTEM CLOCK W 26M 19P2M 13M 12P288M 12M 11P2896M — 256F
S
0x00
0x05 SAMPLE RATE W — — SR_96K SR_32K SR_48K SR_44K1 SR_16K SR_8K 0x00
0x06 DAI INTERFACE W — — RJ_M RJ_S LJ_M LJ_S I2S_M I2S_S 0x00
0x07 DAC PATH W DIG2_HP
DIG2_
EAR
DIG2_
SPK
DIG2_
LOUT
— — — — 0x00
0x08
MIC/DIRECT TO
ADC
W IN12_MIC1
IN34_
MIC2
— —
IN12_
DADC
IN34_
DADC
IN56_
DADC
— 0x00
0x09 LINE TO ADC W IN12S_AB IN34S_AB IN56S_AB IN34D_A IN65D_B — — — 0x00
0x0A ANALOG MIC LOOP W
IN12_
M1HPL
IN12_
M1SPKL
IN12_
M1EAR
IN12_
M1LOUTL
IN34_
M2HPR
IN34_
M2SPKR
IN34_
M2EAR
IN34_
M2LOUTR
0x00
0x0B
ANALOG LINE
LOOP
W
IN12S_
ABHP
IN34D_
ASPKL
IN34D_
AEAR
IN12S_
ABLOUT
IN34S_
ABHP
IN65D
_BSPKR
IN65D_
BEAR
IN34S_
ABLOUT
0x00
RESERVED REGISTER
0x0C RESERVED — — — — — — — — — 0x00
ANALOG INPUT CONFIGURATION REGISTERS
0x0D
LINE INPUT
CONFIG.
R/W IN34DIFF IN65DIFF IN1SEEN IN2SEEN IN3SEEN IN4SEEN IN5SEEN IN6SEEN 0x00
0x0E LINE INPUT LEVEL R/W MIXG135 MIXG246 LINAPGA[2:0] LINBPGA[2:0] 0x1B
0x0F INPUT MODE R/W EXTBUFA EXTBUFB — — — — EXT_MIC[1:0] 0x00
0x10 MIC1 INPUT LEVEL R/W — PA1EN[1:0] PGAM1[4:0] 0x14
0x11 MIC2 INPUT LEVEL R/W — PA2EN[1:0] PGAM2[4:0] 0x14
MICROPHONE CONFIGURATION REGISTERS
0x12 MIC BIAS VOLTAGE R/W — — — — — — MBVSEL[1:0] 0x00
0x13
DIGITAL MIC
ENABLE
R/W — MICCLK[2:0] — — DIGMICR DIGMICL 0x00
0x14
DIGITAL MIC
CONFIG.
R/W DMIC_COMP[3:0] — — DMIC_FREQ[1:0] 0x00