Datasheet

Maxim Integrated │ 6
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Figure 39. Conventional vs. DirectDrive Headphone Output Bias ...................................... 139
Figure 40. Class H Amplifier Charge Pump Operating Ranges ........................................ 140
Figure 41. Class H Amplifier Supply Range Transitions ...............................................141
Figure 42. Zero-Crossing Detection...............................................................141
Figure 43. Block Diagram and Typical Application Circuit for Jack Detection ............................. 143
Figure 44. Jack Detection Cases with Internal Pullup Resistance ...................................... 145
Figure 45. Jack Detection Operation with External Pullup Resistance ....................................147
Figure 46. Jack Detection with Internal Analog Microphones .......................................... 148
Figure 47. START, STOP, and REPEATED START Conditions......................................... 155
Figure 48. Acknowledge Timing................................................................. 156
Figure 49. Writing One Byte of Data to the MAX98090 .............................................. 156
Figure 50. Writing n-Bytes of Data to the MAX98090................................................ 156
Figure 51. Reading One Byte of Data from the MAX98090 ........................................... 157
Figure 52. Reading n-Bytes of Data from the MAX98090 ............................................ 157
Figure 53. Typical Application Circuit with Analog Microphone Inputs and Receiver Output .................. 158
Figure 54. Typical Application Circuit with Digital Microphone Input and Stereo Line Outputs ................ 159
Figure 55. Optional Class D Ferrite Bead EMI Filter................................................. 162
Figure 56. Optional Class H Output RMI Filter..................................................... 162
Figure 57. PCB Breakout Routing Example for WLP Package ......................................... 163
Figure 58. WLP Package Ball Dimensions ........................................................ 164
Table 1. MAX98090 Control Register Map ......................................................... 69
Table 2. Software Reset Register ................................................................ 76
Table 3. Bias Control Register ................................................................... 77
Table 4. DAC and Headphone Performance Mode Control Register ..................................... 77
Table 5. ADC Performance Mode Control Register................................................... 78
Table 6. Device Shutdown Register............................................................... 78
Table 7. Input Enable Register ................................................................... 79
Table 8. Output Enable Register ................................................................. 80
Table 9. Microphone 1 Enable and Level Configuration Register ........................................ 83
Table 10. Microphone 2 Enable and Level Configuration Register ....................................... 83
Table 11. Microphone Bias Level Configuration Register .............................................. 85
Table 12. Digital Microphone Clocks for Commonly Used Master Clocks Settings .......................... 85
Table 13. Digital Microphone Enable .............................................................. 85
Table 14. Digital Microphone Configuration......................................................... 86
Table 15. Recommended Compensation Filter Settings for f
MCLK
= 11.2896MHz.......................... 87
LIST OF FIGURES (continued)
LIST OF TABLES