Datasheet

Maxim Integrated │ 157
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Table 85. Device Status Interrupt Register
Device Status Flags
The device uses register 0x01 (Table 85) and IRQ to report
the status of various device functions. The status register
bits are set when their respective events occur, and cleared
upon reading the register. Device status can be determined
either by polling register 0x01, or by configuring IRQ to pull
low when specific events occur. IRQ is an open-drain out-
put that requires a pullup resistor (10kΩ nominal) for proper
operation. When first exiting shutdown (into normal opera-
tion), other status flags may assert based on the device
settings, register sequencing, and clock sequencing.
Status Flag Masking
Register 0x03, the device status interrupt mask register
(Table 86) determines which bits in the device status inter-
rupt register (Table 85) can trigger a hardware interrupt
ADDRESS: 0x01
DESCRIPTION
BIT NAME TYPE POR
7 CLD CoR 0
Clipping Detect Flag
0: No clipping has occurred.
1: Digital record / playback clipping has occurred.
CLD asserts when the digital record or playback path is clipping due to signal amplitude
exceeding full-scale. This condition is detected at the record path gain control output
(AVLG/AVRG), the playback path gain control output (DVG), and the parametric equalizer
output. To resolve, adjust the gain settings near these detection points.
6 SLD CoR 0
Slew Level Detect Flag
0: No volume slewing sequences have completed.
1: All volume / level slewing complete.
SLD asserts when any one (or more) of the programmable-gain analog output volume
controllers or digital level control arrays has completed slewing from a previous setting
to a new programmed setting. If multiple settings are changed at the same time, in either
the analog or digital domain, the SLD ag will assert only after the last slew is completed.
SLD also asserts when the serial interface soft-start or soft-stop process has completed.
5 ULK CoR 0
Digital Audio Interface (DAI) Phase Locked Loop (PLL) Unlock Flag
0: PLL is locked (if enabled and operating properly).
1: PLL is not locked (if enabled and operating properly).
ULK reports that the digital audio phase-locked loop for DAI is not locked. This condition
only occurs in slave mode when the deviation on LRCLK relative to PCLK exceeds the
lock on range (approximately 4 PCLK periods). This condition can also occur if PCLK
is running and LRCLK has been stopped outside of shutdown. Deviation in BCLK (or
shutting it down) will never trigger a ULK assertion. DAI input and output data may not be
processed / clocked correctly if a ULK event occurs.
4 — — — —
3 — — — —
2 JDET CoR 0
Jack Conguration Change Flag
0: No change in jack conguration.
1: Jack conguration has changed.
JDET asserts anytime jack detection is enabled, and either LSNS or JKSNS changes
state (Table 78). If jack detection is enabled, JDET will assert correctly even while the
device is in the shutdown state. This allows JDET to generate wake on insert interrupts.
1 DRCACT CoR 0
DRC Compression Flag
0: The DRC is either disabled or not in the compression region.
1: The DRC is operating in the compression region.
0 DRCCLP CoR 0
DRC Clipping Flag
0: The DRC is either disabled or no clipping has occurred.
1: DRC clipping has occurred.