Datasheet

Maxim Integrated │ 147
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Figure 43. Block Diagram and Typical Application Circuit for Jack Detection
Jack Detection
The device features a flexible, software configurable
jack detection interface. Once enabled, the jack detec-
tion interface uses two internal comparators to sense the
insertion/removal of a jack and identify the type of jack
inserted (headphones or headset). When the device is in
shutdown or the microphone bias is disabled, the com-
parator thresholds are referenced to V
SPKLVDD
. When
the device is active and microphone bias is enabled, the
comparator thresholds are referenced to V
MICBIAS
.
Jack detection operation relies on a pullup resistance
to set the bias when no jack is inserted. When the
device is in shutdown mode or the microphone bias is
disabled (MICBIAS is high impedance), an internal pul-
lup is enabled on JACKSNS, and is referenced to the
SPKLVDD supply. When the device is not in shutdown
and the microphone bias is enabled, the internal pullup
is disabled (JACKSNS is high impedance). In this state,
successful jack detection requires an external pullup
on JACKSNS to MICBIAS. The jack detection internal
interface structure and typical external application circuit
is shown in Figure 43.
HPSNS
HPR
HPL
MICBIAS
ANALOG
MIC INPUT
LOAD SENSE
COMPARATOR
JACK SENSE
COMPARATOR
V
IN+
JDETEN
JDWK
JDETEN
JDEB[1:0]
INTERNAL
PULL-UP
CONTROL
V
IN-
JACKSNS
LSNS
JKSNS
V
SPKLVDD
V
MICBIAS
V
TH
95%
V
TH
10%
V
SPKLVDD
V
MICBIAS
2.2kΩ
1µF
1µF
1µF
MBEN
V
SPKLVDD
GND LEFTMIC RIGHT