Datasheet

Maxim Integrated │ 114
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
DAI Digital Audio Data Format
The serial data interface supports multiple pulse code mod-
ulated (PCM) digital audio formats including I
2
S, left justi-
fied, right justified, and time division multiplexed (TDM). If
TDM mode is enabled, it takes precedence and the DAI
data is in TDM format. In this case, all non-TDM digital
audio data format configuration registers have no effect.
If TDM mode is disabled, then the data format is deter-
mined by the configuration selected by the control bits
detailed in Table 46. These settings can be used to
change the DAI data format to several supported stan-
dards such as I
2
S (Figure 19), left justified (Figure 20)
or right justified (Figure 21). In addition, the configuration
settings can be enabled or disabled independently, allow-
ing the device to support many nonstandard data format
variations.
Table 46. Digital Audio Interface (DAI) Format Configuration Register
ADDRESS: 0x22
DESCRIPTION
BIT NAME TYPE POR
7 — — — —
6 — — — —
5 RJ R/W 0
Congures the DAI for Right Justied Mode (No Data Delay)
0: Left justied mode enabled with optional data delay.
1: Right justied mode enabled. DLY register is not used and BSEL[2:0] is used
to determine the timing (see the DAI Clock Control and Conguration section for
details).
Note: TDM has priority over all other data formats.
4 WCI R/W 0
Congures the DAI for Frame Clock (LRCLK) Inversion
TDM = 0:
1: Right-channel data is transmitted while LRCLK is low.
0: Left-channel data is transmitted while LRCLK is low.
TDM = 1:
0: Start of a new frame is signied by the rising edge of the LRCLK pulse.
1: Start of a new frame is signied by the falling edge of the LRCLK pulse.
3 BCI R/W 0
Congures the DAI for Bit Clock (BCLK) Inversion
1: SDIN is accepted on the falling edge of BCLK.
0: SDIN is accepted on the rising edge of BCLK.
Master Mode:
1: LRCLK transitions occur on the rising edge of BCLK.
0: LRCLK transitions occur on the falling edge of BCLK.
2 DLY R/W 0
Congures the DAI for Data Delay (I
2
S Standard)
1: The most signicant bit of an audio word is latched at the second BCLK edge
after the LRCLK transition.
0: The most signicant bit of an audio word is latched at the rst BCLK edge after
the LRCLK transition.
Set DLY = 1 to conform to the I
2
S standard. DLY is only effective when TDM = 0.
1
WS[1:0] R/W
0
DAI Input Data Word Size (TDM = 0)
If RJ = 1:
00: 16 bits 01: 20 bits 10: 24 bits 11: Reserved
If RJ = 0:
00: 16 bits 01, 10, 11: 20 bits
0 0