Datasheet

Maxim Integrated │ 111
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
DAI Digital Audio Data Path Control
and Routing
The digital audio data path section supports a variety of
stereo data path configurations and formats (Figure 17).
The standard configuration is to route either the record
path digital audio output to the serial data output (record
path to SDOUT) or to route the serial data input to the dig-
ital audio playback path (SDIN to playback path). These
two primary configurations can be used either individually
or together as needed by the application.
The DAI data path also supports two loop configurations.
Loop back mode takes the digital audio serial data input
and routes it back to the serial data output (SDIN to
SDOUT). Loop through mode allows the record path audio
data output to be looped through to the digital audio play-
back path (and can be combined with the record path to
SDOUT configuration if desired). The configuration settings
for all valid data path combinations are detailed in
Table 44 and are illustrated in Figure 18.
SDOUT can be configured to go to either a high imped-
ance state or to drive a valid logic level (LSB) after all
data bits have been transmitted. When high impedance
mode is enabled, SDOUT goes to a high-impedance state
quickly after the BCLK edge for the LSB occurs to avoid
potential bus contention. SDIN/loopthrough audio data
can be routed through the playback path input mixer as
either stereo audio data, or as a mono representation of
the input audio data. By default, playback mono mode is
disabled and the left/right input audio data is routed to
the left/right playback channels respectively. If playback
mono mode is enabled, the input audio data channels are
reduced in amplitude by 6dB, mixed together (summed),
and then routed to both the left and right record path
channels. The full list of DAI data path configuration con-
trol bits are detailed in Table 45.
Figure 17. DAI Digital Data Path Configuration
PRESCALED
CLOCK
GENERATION
FRAME
CLOCK
BIT
CLOCK
BCI
WCI
MAS
MCLK LRCLK
CLOCK GENERATION AND DISTRIBUTION
BCLK
DAI: CLOCK CONTROL
AND CONFIGURATION
PSCLK[1:0]
PCLK
FREQ[3:0]
USE_MI
NI[14:0]
MI[14:0]
MAX98090
BSEL[2:0]
DIGITAL MIC CLOCK
CONFIGURATION
L/R AUDIO
OUTPUT
RECORD PATH DSP
SDOUT SDIN
L/R AUDIO
INPUT
PLAYBACK PATH DSP
DATA OUTPUT
ENABLE
OUTPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
DATA INPUT
ENABLE
PLAYBACK
INPUT MIXER
LOOP
BACK MUX
LOOP
THROUGH
MUX
SDOEN
HIZOFF
RJ, DLY
WS[1:0]
TDM, FSW
SLOTDLY[3:0]
SLOTL/R[1:0]
DAI: DATA PATH
LTEN
1
01
0
DMONO
SDIENLBEN
RECORD PATH
CLOCKS
PLAYBACK PATH
CLOCKS