Datasheet

Maxim Integrated │ 107
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
In master mode, the device provides three clock operating
modes. In reality all three modes operate in exactly the
same manner (using an internal MI and NI ratio to create
LRCLK). However, the first two modes will internally set
NI and MI automatically and are provided as configura-
tion shortcuts for commonly used PCLK to LRCLK ratios.
The three operating modes are detailed below, and are
presented in order of activation priority.
Quick Conguration Mode
In quick configuration mode, the master clock frequency
(Table 36) and sample rate (Table 37) are selected from
a list of commonly used frequencies. Only a single bit in
each quick setup register can be enabled at any given
time. Quick configuration mode is activated anytime
that both a master clock frequency quick setup bit and
a sample rate quick setup bit are concurrently enabled.
Once enabled, this mode supersedes both of the other
operating modes and an internal preset ratio for NI and
MI is used to create LRCLK. As a result, when Quick
Configuration Mode is enabled the exact integer mode
settings (Table 39), and the manual ratio mode settings
(Tables 40 to 43) are preserved but ignored. If this mode
is later disabled, the preserved settings of any active
lower precedence modes reassert.
To ensure that the DSP is optimally configured and that all
timing requirements are met, when using quick configura-
tion mode the master clock divider (PSCLK, Table 34),
digital filters (MODE, Table 27), and ADC oversampling
rate (OSR128, Table 5) are automatically configured.
While in quick configuration mode these registers are
Table 36. Master Clock Quick Setup Register
Table 37. Sample Rate Quick Setup Register
ADDRESS: 0x04
DESCRIPTION
BIT NAME TYPE POR
7 26M R/W 0 Setup device for operation with a 26MHz master clock (MCLK).
6 19P2M R/W 0 Setup device for operation with a 19.2MHz master clock (MCLK).
5 13M R/W 0 Setup device for operation with a 13MHz master clock (MCLK).
4 12P288M R/W 0 Setup device for operation with a 12.288MHz master clock (MCLK).
3 12M R/W 0 Setup device for operation with a 12MHz master clock (MCLK).
2 11P2896M R/W 0 Setup device for operation with a 11.2896MHz master clock (MCLK).
1 — — — —
0 256F
S
R/W 0 Setup device for operation with a 256 x f
S
MHz master clock (MCLK)
ADDRESS: 0x05
DESCRIPTION
BIT NAME TYPE POR
7 — — — —
6 — — — —
5 SR_96K R/W 0 Setup clocks and lters for a 96kHz sample rate.
4 SR_32K R/W 0 Setup clocks and lters for a 32kHz sample fate.
3 SR_48K R/W 0 Setup clocks and lters for a 48kHz sample rate.
2 SR_44K1 R/W 0 Setup clocks and lters for a 44.1kHz sample rate.
1 SR_16K R/W 0 Setup clocks and lters for a 16kHz sample rate.
0 SR_8K R/W 0 Setup clocks and lters for an 8kHz sample rate.