Datasheet
Maxim Integrated
│
106
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Table 34. System Master Clock (MCLK) Prescaler Configuration Register
Table 35. Master Mode Clock Configuration Register
then no valid clock output is present. In addition to this,
the device does not generate any clocks unless at least
one valid digital audio data path is enabled (ADC record,
DAC playback, digital microphone input, etc.).
In master mode, the device uses two integer values (NI
and MI) as a multiplier and divider (respectively) to scale
PCLK into LRCLK. BCLK is then created either from a
PCLK divider or from an LRCLK multiplier (Table 35).
Based on the oversampling rate selected (OSR, see the
ADC Functional Configuration section), and the config-
ured NI/MI ratio, the output LRCLK frequency is calcu-
lated with the following relationship:
LRCLK PCLK
NI
ff
MI OSR
= ×
×
This expression illustrates that in master mode, the rela-
tionship between LRCLK and PCLK frequency (as well as
BCLK) is based on an integer ratio. As a result, any cycle
to cycle jitter or absolute frequency variation in MCLK
is translated first into PCLK and then into LRCLK (and
BCLK) based on the selected clock ratios.
ADDRESS: 0x1B
DESCRIPTION
BIT NAME TYPE POR
7 — — — —
6 — — — —
5
PSCLK[1:0] R/W
0
Master Clock (MCLK) Prescaler Conguration
00: Internal master clock generation disabled
01: f
PCLK
= f
MCLK
/1, 10MHz ≤ f
MCLK
≤ 20MHz
10: f
PCLK
= f
MCLK
/2, 20MHz < f
MCLK
≤ 40MHz
11: f
PCLK
= f
MCLK
/4, 40MHz < f
MCLK
≤ 60MHz
4 0
3 — — — —
2 — — — —
1 — — — —
0 — — — —
ADDRESS: 0x21
DESCRIPTION
BIT NAME TYPE POR
7 MAS R/W 0
Master Mode Enable
0: Slave mode
(LRCLK/BCLK are inputs and accept external clock sources).
1: Master mode
(LRCLK/BCLK are outputs and timing signals are generated internally).
6 — — — —
5 — — — —
4 — — — —
3 — — — —
2
BSEL[2:0] R/W
0
Bit Clock (BCLK) Conguration (Master Mode/Slave Right Justied Only)
000: Bit clock disabled 100: f
BCLK
= f
PCLK
/2
001: f
BCLK
= 32 x f
S
101: f
BCLK
= f
PCLK
/4
010: f
BCLK
= 48 x f
S
110: f
BCLK
= f
PCLK
/8
011: f
BCLK
= 64 x f
S
111: f
BCLK
= f
PCLK
/16
1 0
0 0