Datasheet

Maxim Integrated │ 105
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Figure 16. DAI Clock Control and Configuration Section
DAI Clock Control and Conguration
The clock control and configuration section is one of the
two major blocks in the digital audio interface (Figure 16).
This section is responsible for accepting and scaling the
device master clock, for internal digital clock generation,
and for digital audio interface data clocking and timing.
The device can accept an external master clock (MCLK)
with a frequency ranging from 10MHz to 60MHz. However,
for digital operation, signal processing, and data conver-
sion the device requires an internal clock between 10MHz
and 20MHz. To generate an internal master clock within
this frequency range, an internal clock divider is used
(Table 34). The internal clock divider can be set to fre-
quency divide MCLK by a factor 1, 2, or 4 to create the
internal prescaled master clock (PCLK). PCLK is then
used, either directly or through additional divider/multiplier
blocks, to clock all internal digital sections.
The digital audio interface signal paths support any sam-
pling rate from 8kHz to 96kHz. The device has only a single
DAI, and as a result both the record (output) and playback
(input) digital audio paths use the same sampling rate.
The device digital audio interface supports both master
and slave mode operation (Table 35). To properly time
the serial data input (SDIN) and output (SDOUT), the
DAI requires both a left-right frame clock (LRCLK) and a
bit clock (BCLK). In master mode, the device uses one
of several modes to generate both LRCLK and BCLK
from the internal prescaled master clock (PCLK). In slave
mode however, both LRCLK and BCLK must be exter-
nally provided.
Master Mode Clock Conguration
When the device is configured as the digital audio mas-
ter, the frame clock (LRCLK) and bit clock (BCLK) are
configured as outputs and the device uses the internal
prescaled master clock (PCLK) to create them.
If no clock outputs or unexpected clock outputs are mea-
sured on LRCLK and/or BCLK, verify that the device is not
in shutdown and that all three clocks are configured cor-
rectly. If the master clock prescale value is not selected
(PSCLK[1:0]), the clock ratio is not fully configured (oper-
ating mode), or if the bit clock rate is not set (BSEL[2:0])
PRESCALED
CLOCK
GENERATION
FRAME
CLOCK
BIT
CLOCK
BCI
WCI
MAS
MCLK LRCLK
CLOCK GENERATION AND DISTRIBUTION
BCLK
DAI: CLOCK CONTROL
AND CONFIGURATION
DIGITAL MIC CLOCK
CONFIGURATION
L/R AUDIO
OUTPUT
RECORD PATH DSP
PSCLK[1:0]
PCLK
SDOUT SDIN
FREQ[3:0]
USE_MI
NI[14:0]
MI[14:0]
MAX98090
L/R AUDIO
INPUT
PLAYBACK PATH DSP
BSEL[2:0]
DATA OUTPUT
ENABLE
OUTPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
DATA INPUT
ENABLE
PLAYBACK
INPUT MIXER
LOOP
BACK MUX
LOOP
THROUGH
MUX
SDOEN
HIZOFF
RJ, DLY
WS[1:0]
TDM, FSW
SLOTDLY[3:0]
SLOTL/R[1:0]
DAI: DATA PATH
LTEN
1
01
0
DMONO
SDIENLBEN
RECORD PATH
CLOCKS
PLAYBACK PATH
CLOCKS