Datasheet
Maxim Integrated
│
104
MAX98090 Ultra-Low Power Stereo Audio Codec
www.maximintegrated.com
Figure 15. Simplified Digital Audio Interface Block Diagram
Digital Audio Interface (DAI) Conguration
The digital audio interface (DAI) contains two primary sec-
tions (Figure 15). The first is the clock control and configu-
ration section. The device supports both master and slave
mode operation, can accept a master clock of either 256
x f
S
or ranging from 10MHz to 60MHz, and can be config-
ured for any digital audio sampling rate (f
S
) from 8kHz to
96kHz. When the device is configured as the digital audio
master, a variety of operating modes are available. These
include a simple quick configuration mode, exact integer
sampling mode, and a manual clock divider mode. When
the device is configured to slave mode, the internal PLL
quickly locks onto the external LRCLK frequency.
The second section is the digital audio data path control
and signal routing. This section supports a variety of ste-
reo data path configurations including serial audio input
and output, audio loop through from the record to play-
back paths, and audio loop back from the serial data input
to the serial data output. The serial data interface also
supports several standard digital audio formats (PCM)
including I
2
S, left justified, right justified, and time division
multiplexed (TDM).
PRESCALED
CLOCK
GENERATION
FRAME
CLOCK
BIT
CLOCK
DATA OUTPUT
ENABLE
OUTPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
DATA INPUT
ENABLE
PLAYBACK
INPUT MIXER
LOOP
BACK MUX
LOOP
THROUGH
MUX
SDOEN
HIZOFF
RJ, DLY
WS[1:0]
TDM, FSW
SLOTDLY[3:0]
SLOTL/R[1:0]
BCI
WCI
MAS
MCLK LRCLK
CLOCK GENERATION AND DISTRIBUTION
BCLK
DAI: CLOCK CONTROL
AND CONFIGURATION DAI: DATA PATH
DIGITAL MIC CLOCK
CONFIGURATION
L/R AUDIO
OUTPUT
RECORD PATH DSP
PSCLK[1:0]
PCLK
SDOUT SDIN
LTEN
1
01
0
DMONO
SDIENLBEN
FREQ[3:0]
USE_MI
NI[14:0]
MI[14:0]
MAX98090
L/R AUDIO
INPUT
PLAYBACK PATH DSP
BSEL[2:0]
RECORD PATH
CLOCKS
PLAYBACK PATH
CLOCKS