Datasheet
MAX9744
Supply Bypassing, Layout,
and Grounding
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Large traces also aid in mov-
ing heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Connect PGND and
GND together at a single point on the PCB. Route all
traces that carry switching transients away from GND
and the traces/components in the audio signal path.
Connect all PVDD power supplies together and bypass
with a 1µF capacitor to PGND. Connect all V
DD
power
supplies together and bypass with a 1µF capacitor to
GND. Place a bulk capacitor between PVDD and PGND
if needed.
Use large, low-resistance output traces. Current drawn
from the outputs increase as load impedance decreas-
es. High output trace resistance decreases the power
delivered to the load. Large output, supply, and GND
traces allow more heat to move from the MAX9744 to
the air, decreasing the thermal impedance of the circuit.
The MAX9744 thin QFN package features an exposed
thermal pad on its underside. This pad lowers the pack-
age’s thermal resistance by providing a direct heat con-
duction path from the die to the PCB. Connect the
exposed thermal pad to PGND by using a large pad and
multiple vias to the PGND plane. The exposed pad must
be connected to PGND for proper device operation.
20W Stereo Class D Speaker Amplifier
with Volume Control
______________________________________________________________________________________ 23
TOP VIEW
MAX9744
TQFN
(7mm x 7mm)
12
13
14
15
16
17
18
19
20
21
22
GND
ADDR1
ADDR2
GND
INL
FBL
FBR
INR
BIAS
V
DD
SHDN
44
43
42
41
40
39
+
38
37
36
35
34
1
2
345
678910
11
PGND
PGND
OUTL-
OUTL-
BOOTL-
PGND
BOOTR-
OUTR-
OUTR-
PGND
PGND
GND
V
DD
SCLK/PWM
SDA/VOL
GND
V
DD
PVDD
PVDD
OUTL+
OUTL+
BOOTL+
33
32
31 30 29 28 27 26 25 24
23
N.C.
MUTE
SYNC
SYNCOUT
GND
V
DD
PVDD
PVDD
OUTR+
OUTR+
BOOTR+
Pin Configuration