Datasheet

MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
______________________________________________________________________________________ 17
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions section). SDA and SCL idle high when the
I
2
C bus is not busy.
START and STOP Conditions
A master device initiates communication by issuing a
START condition. A START condition is a high to low
transition on SDA with SCL high. A STOP condition is a
low to high transition on SDA while SCL is high (Figure
4). A START (S) condition from the master signals the
beginning of a transmission to the MAX9744. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP (P) condition. The bus remains active if a
Repeated START (Sr) condition is generated instead of
a STOP condition.
Early STOP Conditions
The MAX9744 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Slave Address
The slave address of the MAX9744 is 8 bits and con-
sists of 3 fields: the first field is 5 bits wide and is fixed
(10010), the second is a 2 bit field which is set through
ADDR1 and ADDR2 (externally connected as logic-high
or logic-low), and the third field is a R/W flag bit. Set
R/W = 0 to write to the slave. A representation of the
slave address is shown in Table 3.
When ADDR1 and ADDR2 are connected to GND, seri-
al interface communication is disabled. Table 4 sum-
marizes the slave address of the device as a function of
ADDR1 and ADDR2.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9744 uses to handshake receipt of each byte of
data (see Figure 5). The MAX9744 pulls down SDA dur-
ing the master-generated 9th clock pulse. The SDA line
must remain stable and low during the high period of
the acknowledge clock pulse. Monitoring ACK allows
for detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master may reat-
tempt communication.
SCL
SDA
SSrP
Figure 4. START, STOP, and Repeated START Conditions
1
SCL
START
CONDITION
SDA
29
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
8
Figure 5. Acknowledge
SA7 (MSB) SA6 SA5 SA4 SA3 SA2 SA1 SA0 (LSB)
1 0 0 1 0 ADDR2 ADDR1 R/W
Table 3. Slave Address Block
ADDR2 ADDR1 SLAVE ADDRESS
00I
2
C disabled
0 1 1001001_
1 0 1001010_
1 1 1001011_
Table 4. Slave Address