Datasheet

11Maxim Integrated
Differential Input DirectDrive
Line Drivers/Headphone Amplifiers
MAX97220A–MAX97220E
Pin Description
Pin Configuration
15
16
EP
14
13
6
5
7
C1P
C1N
8
PVDD
BIAS SVDD2 OUTL
12
INL-
4
12 11 9
INL+
SHDN
INR-
INR+
SGND
PVSS
MAX97220
PGND OUTR
3
10
SVDD
TQFN
TOP VIEW
+
PIN NAME FUNCTION
1 PVDD
Charge-Pump Power-Supply Input. Bypass to PGND with 1FF.
2 C1P
Positive Flying Capacitor Connection. Connect a 1FF capacitor between C1P and C1N.
3 PGND Power Ground. Connect PGND and SGND together at the system ground plane.
4 C1N
Negative Flying Capacitor Connection. Connect a 1FF capacitor between C1P and C1N.
5 PVSS
Negative Charge-Pump Output. Bypass to PGND with 1FF.
6 SGND Signal Ground. Connect PGND and SGND together at the system ground plane.
7 INR+ Right Positive Polarity Input
8 INR- Right Negative Polarity Input
9 SVDD2
Signal Path Power-Supply Input. Bypass to PGND with 1FF. Connect directly to PVDD.
10 OUTR Right DirectDrive Output
11 BIAS
Internal Supply Node. Bypass to PGND with 0.1FF.
12 OUTL Left DirectDrive Output
13 SVDD
Signal Path Power-Supply Input. Bypass to PGND with 1FF. Connect directly to PVDD.
14 INL- Left Negative Polarity Input
15 INL+ Left Positive Polarity Input
16
SHDN Active-Low Shutdown. Drive SHDN high for normal operation.
— EP Exposed Pad. Electrically connect to PGND or leave unconnected.