Datasheet

Control Register 2
Control Register 2 is an 8-bit write/read register that provides the different time delay options for asserting the comparator
output when monitoring fault events. Tables 6 and 7 show the bit location and function for Control Register 2.
Table 5. Control Register 1 Bit Description
Table 6. Control Register 2
Table 7. Control Register 2 Bit Descriptions
BIT BIT NAME FUNCTION
2, 1, 0
MUX2, MUX1,
MUX0
000 Channel A: Read current-sense amplier output from ADC, gain = 1x
001 Channel A: Read current-sense amplier output from ADC, gain = 4x
010 Channel A: Read current-sense amplier output from ADC, gain = 8x
011 Channel B: Read average voltage of RS+ (input common-mode voltage) from ADC
100 Channel C: Read voltage of OUT from ADC
101 Channel D: Read voltage of SET from ADC
110 Channel E: Read internal die temperature from ADC
111 Read all channels in fast-read mode, sequentially every 2ms. Uses last gain setting.
3 SHDN
Power-on state = 0
0 = Normal operation
1 = Shutdown mode
4 LR
0 = Normal operation
1 = Reset if comparator is latched due to MODE = 111. This bit is automatically reset after a 1
is written.
7, 6, 5
MODE2, MODE1,
MODE0
000 = Normal operation for op amp/comparator
111 = Comparator mode. OUT remains low until CSA output > V
SET
for 1ms, OUT latches
high for 50ms, then OUT autoretries by going low. The comparator has an internal
±10mV hysteresis voltage to help with noise immunity. For MAX9612, the polarity is
reversed.
011 = Op-amp mode. OUT regulates pFET for 1ms at V
SET
, OUT latches high for 50ms,
then OUT autoretries by going low. For MAX9612, the polarity is reversed.
BIT NUMBER 7 6 5 4 3 2 1 0
BIT NAME X X X X DTIM RTIM X X
POR VALUE 0 0 0 0 0 0 0 0
BIT BIT NAME FUNCTION
7, 6, 5, 4 X Set to 0
3 DTIM
Watchdog delay time
0 = 1ms
1 = 100µs
2 RTIM
Watchdog retry delay time
0 = 50ms
1 = 10ms
1, 0 X Set to 0
MAX9611/MAX9612 High-Side, Current-Sense Ampliers with
12-Bit ADC and Op Amp/Comparator
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