Datasheet

Slave Address
A bus master initiates communication with a slave device
by issuing a START (S) condition followed by a slave
address. When idle, the MAX9611/MAX9612 continu-
ously wait for a START condition followed by their slave
address. When the MAX9611/MAX9612 recognize a
slave address, it is ready to accept or send data. The
MAX9611/MAX9612 offer 16 different slave addresses
using two address inputs, A1 and A0. See Table 2 for
different slave address options. The least significant bit
(LSB) of the address byte (R/W) determines whether
the master is writing to or reading from the MAX9611/
MAX9612 (R/W = 0 selects a write condition, R/W = 1
selects a read condition). After receiving the address, the
MAX9611/MAX9612 (slave) issue an acknowledge by
pulling SDA low for one clock cycle.
I
2
C Write Operation
A write operation (Figure 1) begins with the bus master
issuing a START condition followed by seven address bits
and a write bit (R/W = 0). If the address byte is success-
fully received, the MAX9611/MAX9612 (slave) issue an
acknowledge (A). The master then writes to the slave and
the sequence is terminated by a STOP (P) condition for a
single write operation.
For a burst write operation, more data bytes are sent after
the register address before the transaction is terminated.
I
2
C Read Operation
In an I
2
C read operation (Figure 2), the bus master issues
a write command first by initiating a START condition fol-
lowed by seven address bits, a write bit (R/W = 0) and the
8-bit register address. The master then issues a Repeated
START (Sr) condition, followed by seven address bits,
a read bit (R/W = 1). If the address byte is success-
fully received, the MAX9611/MAX9612 (slave) issue an
acknowledge (A). The master then reads from the slave.
For continuous read, the master issues an acknowledge
bit (AM) after each received byte. The master terminates
the read operation by sending a not acknowledge (NA)
bit. The MAX9611/MAX9612 then release the data line
SDA allowing the master to generate a STOP condition.
Table 2. MAX9611/MAX9612 Address
Description
Figure 1. I
2
C Write Operation
Figure 2. I
2
C Read Operation
A1 A0
DEVICE WRITE
ADDRESS (hex)
DEVICE READ
ADDRESS (hex)
0 0 0xE0 0xE1
0 1/3 x V
CC
0xE2 0xE3
0 2/3 x V
CC
0xE4 0xE5
0 V
CC
0xE6 0xE7
1/3 x V
CC
0 0xE8 0xE9
1/3 x V
CC
1/3 x V
CC
0xEA 0xEB
1/3 x V
CC
2/3 x V
CC
0xEC 0xED
1/3 x V
CC
V
CC
0xEE 0xEF
2/3 x V
CC
0 0xF0 0xF1
2/3 x V
CC
1/3 x V
CC
0xF2 0xF3
2/3 x V
CC
2/3 x V
CC
0xF4 0xF5
2/3 x V
CC
V
CC
0xF6 0xF7
V
CC
0 0xF8 0xF9
V
CC
1/3 x V
CC
0xFA 0xFB
V
CC
2/3 x V
CC
0xFC 0xFD
V
CC
V
CC
0xFE 0xFF
SINGLE WRITE
BURST WRITE
REGISTER ADDRESSSLAVE ADDRESSS 0 A
A P
DATA
A A P
ACKNOWLEDGE FROM
MAX9611/MAX9612
R/W
STOP
REGISTER ADDRESS
SLAVE ADDRESSS 0 A
DATA 2DATA 1
A A
DATA N
DATA 3
A A
ACKNOWLEDGE FROM
MAX9611/MAX9612
R/W
STOP
ACKNOWLEDGE FROM
MAX9611/MAX9612
ACKNOWLEDGE FROM
FROM MASTER
SINGLE READ
REGISTER ADDRESS
SLAVE ADDRESS
SLAVE ADDRESS DATA
S
A Sr 1
R/W
0 A
NO READ-ACKNOWLEDGE
FROM MASTER
R/W
A AM P
ACKNOWLEDGE FROM
MAX9611/MAX9612
BURST READ
REPEAT
START
REGISTER ADDRESSSLAVE ADDRESS
SLAVE ADDRESS DATA
S
A Sr 1
R/W
0 A
R/W
A
DATA N
AM NA PAM
DATA
MAX9611/MAX9612 High-Side, Current-Sense Ampliers with
12-Bit ADC and Op Amp/Comparator
www.maximintegrated.com
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