Datasheet
MAX9600/MAX9601/MAX9602
Dual ECL and Dual/Quad PECL, 500ps,
Ultra-High-Speed Comparators
______________________________________________________________________________________ 11
Timing Information (MAX9600/MAX9601)
The timing diagram (Figure 1) illustrates the operation
of a comparator with latch enable. The top line of the
diagram illustrates a latch-enable pulse. Initially, the
latch-enable input (LE, LE_) is differentially high, which
places the comparator in latch mode. When the input
signal (IN_+, IN_-) switches from low to high, the output
(Q_, Q_) remains latched to the previous low state.
When the latch-enable input goes differentially low,
starting the compare function, the output responds to
the input and transitions to high after a time (t
LPD
). The
leading edges of the subsequent input signal switch
the comparator after time interval t
PD+
or t
PD-
(depend-
ing on the direction of the input transitions) until a high
latch-enable pulse places the device in latch mode
again. The input signal must occur at minimum time
(t
LS
) before the latch rising edge, and must maintain its
state for at least t
LH
after the rising edge. A minimum
latch-pulse width (t
LPW
) of 250ps (typ) is needed for
proper latch operation.
ECL/PCL
The MAX9600/MAX9601/MAX9602 outputs are emitter
followers that require external resistive connections to a
voltage source (V
T
) more negative than the lowest V
OL
for proper static and dynamic operation. When properly
terminated, the outputs provide appropriate levels, V
OL
or V
OH
, for ECL (MAX9600) or PECL (MAX9601/
MAX9602). Output-current polarity always sinks into the
termination scheme during proper operation.
ECL-output signal levels are referenced to GND, and
PECL-output signals are referenced to V
CCO
_.
Chip Information
MAX9600 TRANSISTOR COUNT: 558
MAX9601 TRANSISTOR COUNT: 600
MAX9602 TRANSISTOR COUNT: 608
PROCESS: Bipolar
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
QB
QB
V
CCOB
LEBLEA
V
CCOA
QA
QA
LEB
V
EE
V
CC
HYSBHYSA
V
CC
V
EE
LEA
12
11
9
10
INB-
INB+INA+
INA-
MAX9601
TSSOP-20
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
V
CCOA
QA
QA
V
CCOB
INB+
V
EE
INA-
INA+
QB
QB
V
CCOC
QCINC-
INC+
V
CC
INB-
16
15
14
13
9
10
11
12
QC
V
CCOD
QD
QDV
CC
IND-
IND+
V
EE
TSSOP-24
MAX9602
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
QB
QB
GND
LEBLEA
GND
QA
QA
TOP VIEW
LEB
V
EE
V
CC
HYSBHYSA
V
CC
V
EE
LEA
12
11
9
10
INB-
INB+INA+
INA-
MAX9600
TSSOP-20
Pin Configurations