Datasheet

Applications Information
LVPECL Output Termination
Terminate the MAX9376 LVPECL outputs with 50Ω to
(V
CC
- 2V) or use equivalent Thevenin terminations.
Terminate OUT1 and OUT1 with identical termination on
each for low output distortion. When a single-ended signal
is taken from the differential output, terminate both OUT1
and OUT1.
Ensure that output currents do not exceed the current lim-
its as specified in the Absolute Maximum Ratings. Under
all operating conditions, the device's total thermal limits
should be observed.
LVDS Output Termination
The MAX9376 LVDS outputs are current-steering devic-
es; no output voltage is generated without a termination
resistor. The termination resistors should match the differ-
ential impedance of the transmission line. Output voltage
levels are dependent upon the value of the termination
resistor. The MAX9376 is optimized for point-to-point
interface with 100Ω termination resistors at the receiver
inputs. Termination resistance values may range between
90Ω and132Ω, depending on the characteristic imped-
ance of the transmission medium.
Supply Bypassing
Bypass V
CC
to ground with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors. Place the capaci-
tors as close to the device as possible with the 0.01µF
capacitor closest to the device pins.
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the 50Ω
characteristic impedance of the traces. Avoid discontinuities
by maintaining the distance between differential traces, not
using sharp corners or using vias. Maintaining distance
between the traces also increases common-mode noise
immunity. Reducing signal skew is accomplished by
matching the electrical length of the differential traces.
V
CM
(MAX)
V
CC
GND
V
ID
V
CM
(MIN)
V
ID
80%
OUT2 - OUT2
20%
20%
80%
0V
t
F
t
R
DRV
OUT2
OUT2
R
L
/ 2
R
L
/ 2
VOD
VOD(+)
VOD(-)
VOS
GND
C
L
C
L
t
PHL
t
PLH
80%
20%
20%
80%
DIFFERENTIAL OUTPUT
WAVEFORM
V
ID
OR (V
IH
- V
IL
)
V
OD
OR (V
OH
- V
OL
)
+V
OD
OR +(V
OH
- V
OL
)
-V
OD
OR -(V
OH
- V
OL
)
0V DIFFERENTIAL
V
OH
V
OL
0V DIFFERENTIAL
IN
IN
OUT
OUT
OUT - OUT
t
F
t
R
Figure 1. Input Definition
Figure 2. LVDS Output Load and Transition Times
Figure 3. Differential Input-to-Output Propagation Delay Timing
Diagram
www.maximintegrated.com
Maxim Integrated │ 6
MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator