Datasheet

Detailed Description
The MAX9376 is a fully differential, high-speed, LVDS/
anything-to-LVPECL/LVDS dual translator designed
for signal rates up to 2GHz. One channel is LVDS/
anything-to-LVPECL translator and the other channel
is LVDS/anything-to-LVDS translator. The MAX9376's
extremely low propagation delay and high speed make
it ideal for various high-speed network routing and back-
plane applications.
The MAX9376 accepts any differential input signal within
the supply rails and with a minimum amplitude of 100mV.
Inputs are fully compatible with the LVDS, LVPECL,
HSTL, and CML differential signaling standards. LVPECL
outputs have sufficient current to drive 50Ω transmission
lines. LVDS outputs conform to the ANSI EIA/TIA-644
LVDS standard.
Inputs
Inputs have a wide common-mode range of 0.05V to V
CC
- 0.05V, which accommodates any differential signals
within rails, and requires a minimum of 100mV to switch
the outputs. This allows the MAX9376 inputs to support
virtually any differential signaling standard.
LVPECL Outputs
The MAX9376 LVPECL outputs are emitter followers that
require external resistive paths to a voltage source (V
T
=
V
CC
- 2.0V typ) more negative than worst-case V
OL
for
proper static and dynamic operation. When properly ter-
minated, the outputs generate steady-state voltage lev-
els, V
OL
or V
OH
with fast transition edges between state
levels. Output current always flows into the termination
during proper operation.
LVDS Outputs
The MAX9376 LVDS outputs require a resistive load to
terminate the signal and complete the transmission loop.
Because the device switches current and not voltage, the
actual output voltage swing is determined by the value of
the termination resistor. With a 3.5mA typical output cur-
rent, the MAX9376 produces an output voltage of 350mV
when driving a 100Ω load.
PIN NAME FUNCTION
1 IN1 Differential LVDS/Anything Noninverting Input 1
2
IN1
Differential LVDS/Anything Inverting Input 1
3 OUT2
Differential LVDS Noninverting Output 2. Terminate with 100Ω ±1% to OUT2.
4
OUT2
Differential LVDS Inverting Output 2. Terminate with 100Ω ±1% to OUT2.
5 GND Ground
6
IN2
Differential LVDS/Anything Inverting Input 2
7 IN2 Differential LVDS/Anything Noninverting Input 2
8
OUT1
Differential LVPECL Inverting Output. Terminate with 50Ω ±1% to V
CC
- 2V.
9 OUT1 Differential LVPECL Noninverting Output. Terminate with 50Ω ±1% to V
CC
- 2V.
10 V
CC
Positive Supply. Bypass from V
CC
to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Pin Description
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MAX9376 LVDS/Anything-to-LVPECL/LVDS Dual Translator