Datasheet
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
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Detailed Description
The MAX9325 low-skew, 2:8 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make the
device ideal for clock and data distribution across a
backplane or board. The device selects one of the two
differential HSTL or LVECL/LVPECL inputs, and repeats
them at eight differential outputs. Outputs are compati-
ble with LVECL and LVPECL, and can directly drive 50Ω
terminated transmission lines.
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLK_SEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLK_SEL is set by
an internal V
BB
voltage reference. The selected input is
reproduced at eight differential outputs at speeds up to
700MHz.
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output volt-
age (V
BB
). A single-ended input of at least V
BB
±95mV
or a differential input of at least 95mV switches the out-
puts to the V
OH
and V
OL
levels specified in the DC
Electrical Characteristics. The maximum magnitude of
the differential input from CLK_ to CLK_ is ±3.0V or
±(V
CC
- V
EE
), whichever is less. This limit also applies
to the difference between a single-ended input and any
reference voltage input.
The single-ended CLK_SEL input has a 75kΩ pulldown
to V
EE
that selects the default input, CLK0, CLK0, when
CLK_SEL is left open or at V
EE
. All the differential inputs
have 105kΩ pulldowns to V
EE
. Internal pulldowns and a
fail-safe circuit ensure differential low default outputs
when the inputs are left open or at V
EE
.
Specifications for the high and low voltages of a differ-
ential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.375V to +3.8V supply
range, allowing high-performance clock or data distrib-
ution in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.375V to -3.8V supply.
Single-Ended Operation
CLK_SEL is a single-ended input with the input threshold
internally set to V
BB
, and can be driven to V
CC
or V
EE
or
by a single-ended LVPECL/LVECL signal. The CLK_,
CLK_ are differential inputs but can be configured to
accept single-ended inputs when operating at supply
voltages greater than 2.58V. The recommended supply
voltage for single-ended operation is 3.0V to 3.8V. A dif-
OR
V
BB
V
BB
V
BB
V
BB
t
PLH
t
PHL
V
OH
- V
OL
Q_
Q_
CLK_ WHEN CLK_ = V
BB
V
OH
V
IL
V
IL
V
IH
V
IH
V
OL
CLK_ WHEN CLK_ = V
BB
Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram